Runahead execution: an alternative to very large instruction windows for out-of-order processors

By Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt. The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings., 2003

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A Case for MLP-Aware Cache Replacement (2006, background): “However, traditional cache replacement is not aware of the MLP-dependent cost differential between different misses.”
A scalable processing-in-memory accelerator for parallel graph processing (2015, methodology): “Our comprehensive evaluations using five state-of-the-art graph processing workloads with large real-world graphs show that the proposed architecture improves average system performance by a factor of ten and achieves 87% average energy reduction over conventional systems.”
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (2008, background): “Techniques like out-of-o rder execution [40], non-blocking caches [15], and runahead execut ion [5, 23] strive to overlap the latency of future DRAM accesses with th e current access so that the processor does not need to stall (long ) for future DRAM accesses.”
A case for exploiting subarray-level parallelism (SALP) in DRAM (2012, background): “, out-of-order execution [60], non-blocking caches [27], fine-grained multithreading [52, 58], runahead execution [5, 39] and other memory-level parallelism mechanisms [4, 45]).”