Sangyeun Cho

Hardware and Architecture · 2006–2016

A researcher in the Science corpus: 4 papers; trusts 17 researchers and is trusted by 6 researchers here, as inferred from the citation graph.

Subfields

• Hardware and Architecture — 19 citations into it; #603 of 1,551 by trust here, #993 by citations
• Computer Networks and Communications — 18 citations into it; #6,576 of 9,886 by trust here, #5,961 by citations
• Electrical and Electronic Engineering — 9 citations into it; #9,531 of 16,539 by trust here, #15,621 by citations
• Materials Chemistry — 5 citations into it; #6,354 of 11,513 by trust here, #11,278 by citations

Whom Sangyeun Cho trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

1. Stefan K. Lai
2. Bradford M. Beckmann
3. Todd M. Austin
4. Zeshan A. Chishti
5. Benjamin C. Lee
6. Ping Zhou
7. Chi-Keung Luk
8. David A. Wood
9. Simone Raoux
10. Vijayalakshmi Srinivasan

Who trusts Sangyeun Cho overall

1. Sergey Zhuravlev
2. Luiz E. Ramos
3. Cong Xu
4. Sergey Blagodurov
5. Eugene Gorbatov
6. Thomas Moscibroda
7. Jichuan Chang
8. Dimin Niu
9. Alexandra Fedorova
10. Ricardo Bianchini

Papers from Sangyeun Cho's perspective

Ordered by how strongly the researchers Sangyeun Cho trusts endorse each paper. Same corpus, a different order for every researcher.

1. Current status of the phase change memory and its future (IEEE International Electron Devices Meeting 2003)
2. A durable and energy efficient main memory using phase change memory technology (International Symposium on Computer Architecture)
3. Scalable high performance main memory system using phase-change memory technology (International Symposium on Computer Architecture)
4. Architecting phase change memory as a scalable dram alternative (International Symposium on Computer Architecture)
5. An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (ASPLOS X)
6. Managing Wire Delay in Large Chip-Multiprocessor Caches (Micro)
7. Phase-change random access memory: A scalable technology (IBM Journal of Research and Development)
8. Niagara: a 32-way multithreaded Sparc processor (IEEE Micro)
9. Predicting inter-thread cache contention on a chip multi-processor architecture (International Symposium on High-Performance Computer Architecture)
10. Optimizing replication, communication, and capacity allocation in CMPs (International Symposium on Computer Architecture)

Their papers

• Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance (2009) — 564 citations
• Biscuit: A Framework for Near-Data Processing of Big Data Workloads (2016) — 309 citations
• F2FS: A New File System for Flash Storage (2015) — 490 citations
• Managing Distributed, Shared L2 Caches through OS-Level Page Allocation (2006) — 380 citations