A durable and energy efficient main memory using phase change memory technology

By Ping Zhou, Bo Zhao, Jun Yang, Youtao Zhang. International Symposium on Computer Architecture, 2009

954 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture, Materials Chemistry

View Paper: https://www.semanticscholar.org/paper/5454e6e0aceac36e6121a6b0d40d528018f24ab1

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Citations in the corpus

Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory (2011, background): “Additionally, a number of recent studies have identified a slowing of DRAM growth [25] [26] [30] [33] [34] [39] [55] due to scaling challenges for charge-based memories.”
Use ECP, not ECC, for hard failures in resistive memories (2010, background): “Making PCM technology a viable DRAM replacement will require mitigating wear-related failures through architectural enhancements such as write buffers [13, 22], compression schemes [26], wear-leveling mechanisms [21, 22, 26, 27, 28], error-correcting codes [27], or operating system page remapping [1”
Phase-Change Technology and the Future of Main Memory (2010, background): “These alternatives focus on four areas: row buffer design, row caching, wear reduction, and wear leveling.(2,4) Relative to DRAM, these optimizations collectively provide competitive performance, comparable energy, and feasible lifetimes, thus making PCM a viable replacement for main-memory technolo”
Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories (2016, background): “They have showed great potential as candidates of next-generation main memory [15, 28, 27].”
NOVA: A Log-structured File System for Hybrid Volatile/Non-volatile Main Memories (2016, methodology): “…have proposed several approaches to integrating NVMs into computer systems [11] [13] [19] [31] [36] [41] [58] [67], and the most exciting proposals place NVMs on the processor's memory bus alongside conventional DRAM, leading to hybrid volatile/non-volatile main memory systems [4] [51] [72] [78].”
NV-Tree: Reducing Consistency Cost for NVM-based Single Level Systems (2015, background): “Although wear-leveling is necessary for PCM, it can be done by memory controller [48, 61].”
Better I/O through byte-addressable, persistent memory (2009, background): “Finally, several papers have explored the use of PCM as a scal able replacement for DRAM [9, 18, 27] as well as possible wear leveling strategies [18, 27].”
Energy reduction for STT-RAM using early write termination (2009, methodology): “In this paper, we propose Early Write Termination (EWT), a novel technique to signi.cantly reduce write energy with no per formance penalty.”
Persistent B+-Trees in Non-Volatile Main Memory (2015, background): “As a result, there are widespread interests in the research community and in the industry to consider incorporating NVM technologies to substitute or complement DRAM as the main memory in future computer systems [5, 9, 36, 15, 26, 7, 31, 8, 33, 29, 20].”
Approximate storage in solid-state memories (2013, methodology): “PCM and other fast, resistive storage technologies may be used as main memories [21, 36, 47].”
Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance (2009, methodology): “Qureshi et al. examine a hybrid main memory architecture having a DRAM buffer and PRAM main memory.”
Page placement in hybrid memory systems (2011, methodology): “Unt il then, our system can be easily combined with previously prop osed endurance-improvement techniques [8, 18, 20, 38].”
Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling (2009, background): “We show in Figure 17, that our proposal achieves lifetime similar to a hardware unconstrained version of [21] (total overhead 640MB), while requiring 13 bytes overhead and no table-lookup based indirection.”
RowHammer: A Retrospective (2019, background): “[202], [204], [245], [253], [254], [259], STT-MRAM [61], [137], and RRAM/ReRAM/memristors [246] are likely to exhibit similar and perhaps even more exacerbated reliability”
Overcoming the challenges of crossbar resistive memory architectures (2015, methodology): “In addition, the refresh cycle time tRFC increases with the capacity of the DRAM device.”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “A number of Ambit-like bitwise operation substrates have been proposed in recent years, making use of emerging resistive memory technologies, e.g., phasechange memory (PCM) [17, 19, 176, 177, 178, 179], SRAM, or specialized computational DRAM.”