An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches

By Changkyu Kim, Doug Burger, S. Keckler. ASPLOS X, 2002

802 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/fe6c39e17cf18db793586ceb6be36653e402e3d9

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In Computer Networks and Communications

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Citations in the corpus

Managing Wire Delay in Large Chip-Multiprocessor Caches (2004, methodology): “Two, due to the extra freedom of movement, the effectiveness of block migration in a shared CMP cache is more dependent on “smart searches” [27] than its uniprocessor counterpart, yet smart searches are harder to implement in a CMP environment.”
A case for bufferless routing in on-chip networks (2009, methodology): “We model a static non-uniform cache architecture (S-NUCA) [ 26 ] where lower order bits in the address of the cache line determines which bank the cache line resides in. We model all traffic due to instruction and load/store data requests and replies.”
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (2009, methodology): “As the caches capacity and area increase, the wire delay has made the Non-Uniform Cache Access (NUCA) architecture [18] more attractive than the conventional Uniform Cache Access (UCA) one.”
Cooperative Caching for Chip Multiprocessors (2006, methodology): “We choose to compare cooperative caching with victim replication [35] but not other recent CMP caching schemes [6, 7, 17] for several reasons: (1) both victim replication and cooperative caching use cache replacement as the underlying technique to control replication; (2) both schemes are based on a”
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation (2006, background): “The desire to keep more data on chip will lead to a large L2 cache comprising many banks or slices, likely distributed over the chip space [18].”
A NUCA Substrate for Flexible CMP Cache Sharing (2007, positive): “The speci.c layout we propose, based on a non-uniform cache architecture (NUCA) designs, mitigates the e.ects of growing wire resistivity and thus intra-cache communication delays, and permits any degree of cache sharing in this single implementation.”
Hybrid cache architecture with disparate memory technologies (2009, background): “Caches fabricated in these technologies o.er dramatically di.erent power and performance characteristics when compared with SRAMbased caches, particularly in the areas of access latency, cell density, and overall power consumption.”
GARNET: A detailed on-chip network model inside a full-system simulator (2009, methodology): “Target system: We simulated a 64-core CMP with shared L2 distributed in a tiled fashion [16].”
Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors (2005, background): “Both D-NUCA [16] and NuRAPID [6] attempt to reduce average latency for a uniprocessor NUCA cache by migrating frequently-accessed data to cache slices closer to the processor.”