Managing Distributed, Shared L2 Caches through OS-Level Page Allocation
By Sangyeun Cho, Lei Jin. Micro, 2006
380 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/253678be9d08831a62ab608f07f8355312ecbee3
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Computer Networks and Communications
- Onur Mutlu
- Thomas Moscibroda
- James D. Balfour
- John Kim
- William (Bill) J. Dally
- Jichuan Chang
- G. Sohi
- Xiaodong Zhang
In Hardware and Architecture
- Onur Mutlu
- Thomas Moscibroda
- G. Sohi
- Jichuan Chang
- Xiaodong Zhang
- Thomas Eisenbarth
- Sergey Zhuravlev
- Jason Mars
Citations in the corpus
- Flattened Butterfly Topology for On-Chip Networks (2007, background): “For example, in a chip multiprocessor (CMP) architecture with a shared L2 cache distributed across the chip, the L1 miss rate is often under 10% [7], which results in relatively low traffic injection rates at the processors.”
- Cooperative Caching for Chip Multiprocessors (2006, background): “, NUCA substrate [68] and OS-level page mapping [28]).”
- S$A: A Shared Cache Attack That Works across Cores and Defies VM Sandboxing -- and Its Application to AES (2015, background): “Handling Cache Slices: Typically the last level of cache is divided into slices [41], [42], [33].”
- CPI2: CPU performance isolation for shared compute clusters (2013, neutral): “, [35, 36, 9, 42, 4, 32]).”
- Addressing shared resource contention in multicore processors via scheduling (2010, methodology): “Tam, Azimi, Soares and Stumm [24] similarly to several other researchers [6, 14, 15, 27] address cache contention via softwarebased cache partitioning.”
- Bubble-up: Increasing utilization in modern warehouse scale computers via sensible co-locations (2011, background): “Software resource partitioning has also been proposed [6,19,35].”
- Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems (2008, background): “There have been several studies on OS-based cache partitioning policies and their interaction with the micro-architecture support [12, 3].”
- A case for bufferless routing in on-chip networks (2009, background): “For instance, the L1 miss rate i s typically below 10%, which, in a chip multiprocessor with a distributed shared L2 cache, results in very low packet injection rates for the network connecting L1 caches and L2 cache banks [7].”