Niagara: a 32-way multithreaded Sparc processor

By P. Kongetira, K. Aingaran, Kunle Olukotun. IEEE Micro, 2005

1,071 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/7bbe5047739e11e55517428695459a8e2a0484d2

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In Hardware and Architecture

Citations in the corpus

CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques (2011, neutral): “Up to 4 threads share an in-order core pipeline like a Niagara processor [8].”
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (2009, methodology): “In order to predict the chip area, we investigate some die photos, such as Cell Processor [16], Sun UltraSPARC T1 [19], etc. and estimate the area of an 8-core CMP without caches to be 60 mm 2 .”
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation (2006, background): “Processors with two to eight cores are commercially available now [13, 19, 25].”
Technology-Driven, Highly-Scalable Dragonfly Topology (2008, background): “From large scale systems [1, 19, 27] to multicore architectures [17, 33], the interconnection network that connects processors and memory modules significantly impacts the overall performance and cost of the system.”
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006, background): “In particular, our experiments show that a 3D architecture with no dynamic data migration generates better performance than a 2D architecture that employs data migration.”
Managing Wire Delay in Large Chip-Multiprocessor Caches (2004, background): “Larger-scale CMPs seem like to follow as transistor densities increase [5, 18, 45, 28].”
OCEAN (2014, methodology): “138:2 M. M. Sabry et al. At the hardware level, Error Correction Circuitry (ECC) has been widely used in different memory levels [AMD 2001; Mitchell et al. 2005; Kongetira et al. 2005] as ECCs provide single-bit correction with feasible area, energy, and timing overhead.”
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration (2009, background): “…Power and Area Model for Early-Stage Design Space Exploration Andrew B. Kahng , Bin Li+, Li-Shiuan Peh+ and Kambiz Samadi CSE and ECE Departments, University of California, San Diego, La Jolla, CA + EE Department, Princeton University, Princeton, NJ Email: {abk,ksamadi}@ucsd.edu,…”
Larrabee: a many-core x86 architecture for visual computing (2008, background): “Niagara is a multi-core general purpose microprocessor [Kongetira et al. 2005] featuring eight in-order cores, each capable of executing four simultaneous threads, and a shared cache.”
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach (2008, background): “A common way of increasing peak DRAM bandwidth for larger-scale CMP platforms is to integrate multiple memory controllers on chip [22], where each controller serves a diﬀerent set of physical addresses through an independent DRAM channel.”
Cooperative Caching for Chip Multiprocessors (2006, methodology): “Proposed CMP designs [5, 19, 32] have emphasized minimizing the number of off-chip accesses and thus have used a banked, shared L2 cache organization.”
Corona: System Implications of Emerging Nanophotonic Technology (2008, neutral): “The 8- and 16-core Sun Niagara [17] and Niagara2 [24] chips use electrical crossbars.”
Evaluating MapReduce for Multi-core and Multiprocessor Systems (2007, methodology): “The first system (CMP) is based on the UltraSparc T1 multi-core chip with 8 in-order multithreaded cores sharing an L2 cache [19].”
Exploiting coarse-grained task, data, and pipeline parallelism in stream programs (2006, background): “…Programs Michael I. Gordon, William Thies, and Saman Amarasinghe Massachusetts Institute of Technology Computer Science and Arti.cial Intelligence Laboratory {mgordon, thies, saman}@mit.edu Abstract As multicore architectures enter the mainstream, there is a pressing demand for high-level…”