Managing Wire Delay in Large Chip-Multiprocessor Caches

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How researchers see this paper

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Optimizing replication, communication, and capacity allocation in CMPs (2005, methodology): “A recent paper [ 6 ] proposes to alleviate shared cache’s latency by employing nonuniform access.”
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation (2006, methodology): “To overcome the de.ciency, Beckmann and Wood [3] studied a stride-based prefetching technique.”
Cooperative Caching for Chip Multiprocessors (2006, methodology): “Some proposals further use both data migration and replication to optimize important sharing patterns [6, 8], but they require signiﬁcant hardware changes and do not allow adaptive control of such optimizations.”
A NUCA Substrate for Flexible CMP Cache Sharing (2007, methodology): “We evaluated the effect of strided prefetching on the CMP caches by using an implementation similar to the one used by Beckmann and Wood [4].”
Victim replication: maximizing capacity while hiding wire delay in tiled chip multiprocessors (2005, methodology): “There have been several recent proposals [5, 6, 16] to reduce access latency for NUCA caches.”
Hybrid cache architecture with disparate memory technologies (2009, methodology): “In [3], transmission line based NUCA is presented for multi-core design and a prefetch scheme is evaluated for performance improvement.”