Optimizing replication, communication, and capacity allocation in CMPs

By Zeshan A. Chishti, Michael D. Powell, T. N. Vijaykumar. International Symposium on Computer Architecture, 2005

329 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/68e5d22c5c4e4270da8959e8a27b7aeb6820365e

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

In Hardware and Architecture

Citations in the corpus

Hybrid cache architecture with disparate memory technologies (2009, background): “Rapid, is proposed in single core and multi-core designs [7].”
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation (2006, methodology): “For example, with additional hardware support, fine-grained cache line-level data replication [30] and data migration [9] may be employed within our OS-based L2 cache management framework for even higher performance.”
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, background): “Examples of ongoing research in these veins include [5, 6, 10, 11, 12, 15, 19, 20, 21, 22, 33, 44].”
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches (2006, background): “Recent proposals [3][1] have looked at dynamic mechanisms to obtain the hit latency of a private cache while approximating the capacity bene(cid:2)ts of a shared cache.”
A NUCA Substrate for Flexible CMP Cache Sharing (2007, background): “studied optimizations to reduce unnecessary replication and communication overheads [7].”
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (2009, methodology): “Every four cache banks are grouped together and routed to other layers via TSBs. Similar to prior approaches [7, 20], the proposed model supports data migration , which moves data closer to their accessing core.”
Cooperative Caching for Chip Multiprocessors (2006, methodology): “Some proposals further use both data migration and replication to optimize important sharing patterns [6, 8], but they require signiﬁcant hardware changes and do not allow adaptive control of such optimizations.”