Scalable high performance main memory system using phase-change memory technology

By Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers. International Symposium on Computer Architecture, 2009

1,213 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Electronic, Optical and Magnetic Materials, Materials Chemistry

View Paper: https://www.semanticscholar.org/paper/c4bb0e1e263cd184f1de045e323e097224808c9d

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In Electrical and Electronic Engineering

In Electronic, Optical and Magnetic Materials

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Citations in the corpus

Persistent B+-Trees in Non-Volatile Main Memory (2015, background): “As a result, there are widespread interests in the research community and in the industry to consider incorporating NVM technologies to substitute or complement DRAM as the main memory in future computer systems [5, 9, 36, 15, 26, 7, 31, 8, 33, 29, 20].”
Page placement in hybrid memory systems (2011, methodology): “To take advantage of the low latencies of DRAM and the high capacity of PCM, researchers have proposed hybrid memory systems that combine a small amount of DRAM and a large amount of PCM [28, 37, 38].”
Relaxing non-volatility for fast and energy-efficient STT-RAM caches (2011, background): “Spin-Transfer Torque RAM (STT-RAM) is a promising NVM that is actively being developed by industry and that is a potential universal memory technology [6], [11], [17]; Phase-Change Memory (PCM) has already been shown to be a viable candidate for use in main memory [12], [16].”
Phase-Change Technology and the Future of Main Memory (2010, background): “Related work that supports this eort may be found by Qureshi et al. [ 19 ] and Wu et al. [25].”
CACTI 7 (2017, background): “Several works have explored caching policies for such hybrid DRAM/NVM systems (e.g., Qureshi et al. [2009], Ramos et al. [2011], and Yoon et al. [2012b]).”
RowHammer: A Retrospective (2019, background): “Emerging memory technologies [168], [173], such as phase-change memory [141]–[143], [200],”
Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory (2011, background): “Additionally, a number of recent studies have identified a slowing of DRAM growth [25] [26] [30] [33] [34] [39] [55] due to scaling challenges for charge-based memories.”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “A number of Ambit-like bitwise operation substrates have been proposed in recent years, making use of emerging resistive memory technologies, e.g., phasechange memory (PCM) [17, 19, 176, 177, 178, 179], SRAM, or specialized computational DRAM.”
Atlas (2014, background): “Consequently, it is widely expected that alternative, new, and non-volatile memory ( NVRAM ) technologies such as memristors [33] and phase change memory (PCM) [22, 29] will at least par-∗ Figure 1.”
Trends in big data analytics (2014, background): “Other types of NVM such as phase-change memory (PCRAM) and memristors have been proposed to be integrated as byte-addressable memory on the memory bus or stacked directly on the chip (3D-stacking) [82, 72, 83].”
Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance (2009, methodology): “Qureshi et al. examine a hybrid main memory architecture having a DRAM buffer and PRAM main memory.”
NOVA: A Log-structured File System for Hybrid Volatile/Non-volatile Main Memories (2016, methodology): “…have proposed several approaches to integrating NVMs into computer systems [11] [13] [19] [31] [36] [41] [58] [67], and the most exciting proposals place NVMs on the processor's memory bus alongside conventional DRAM, leading to hybrid volatile/non-volatile main memory systems [4] [51] [72] [78].”
Better I/O through byte-addressable, persistent memory (2009, background): “Finally, several papers have explored the use of PCM as a scal able replacement for DRAM [9, 18, 27] as well as possible wear leveling strategies [18, 27].”
Approximate storage in solid-state memories (2013, methodology): “PCM and other fast, resistive storage technologies may be used as main memories [21, 36, 47].”
Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling (2009, background): “[15] propose Fine-Grain Wear Leveling (FGWL) to shift cache lines within a page to achieve uniform wear out of all lines in the page.”