Architecting phase change memory as a scalable dram alternative

By Benjamin C. Lee, Engin Ipek, Onur Mutlu, Doug Burger. International Symposium on Computer Architecture, 2009

1,531 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture, Materials Chemistry

View Paper: https://www.semanticscholar.org/paper/a95436fb5417f16497d90cd2aeb11a0e2873f55f

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Onur Mutlu
2. Hyunjin Lee
3. Sangyeun Cho
4. Shimeng Yu
5. H. Philip Wong
6. Steven Swanson
7. Jian Xu
8. Jeremie S. Kim

In Hardware and Architecture

1. Onur Mutlu
2. Yoongu Kim
3. Jeremie S. Kim
4. Steven Swanson
5. Sangyeun Cho
6. Hyunjin Lee
7. Vivek Seshadri
8. Jian Xu

In Materials Chemistry

1. Onur Mutlu
2. Hyunjin Lee
3. Sangyeun Cho
4. Steven Swanson
5. Jian Xu
6. H. Philip Wong
7. Shimeng Yu
8. Doug Burger

Citations in the corpus

• Evaluating STT-RAM as an energy-efficient main memory alternative (2013, background): “Of these, PCRAM promises substantial density benefits (at least 2-4X over DRAM today), and it has been studied extensively to replace or augment DRAM in building a higher capacity and more scalable main memory system [5], [30], [49], [52], [66], [64].”
• In-Memory Big Data Management and Processing: A Survey (2015, background): “Promisingly, NVRAM can be architected as the main memory in general-purpose systems with well-designed architecture [155], [206], [207].”
• Use ECP, not ECC, for hard failures in resistive memories (2010, background): “…technology a viable DRAM replacement will require mitigating wear-related failures through architectural enhancements such as write buffers [13, 22], compression schemes [26], wear-leveling mechanisms [21, 22, 26, 27, 28], error-correcting codes [27], or operating system page remapping [11, 27, 28].”
• Consistent and Durable Data Structures for Non-Volatile Byte-Addressable Memory (2011, background): “Additionally, a number of recent studies have identified a slowing of DRAM growth [25] [26] [30] [33] [34] [39] [55] due to scaling challenges for charge-based memories.”
• Memory scaling: A systems architecture perspective (2013, methodology): “Yet, row buffer misses are much more costly in terms of latency, bandwidth, and energy in PCM than in DRAM.”
• Overcoming the challenges of crossbar resistive memory architectures (2015, methodology): “In addition, the refresh cycle time tRFC increases with the capacity of the DRAM device.”
• SCMFS: A file system for Storage Class Memory (2011, background): “Some of these solutions improve the lifetime or the performance of PCM devices at the hardware level [12, 13].”
• Better I/O through byte-addressable, persistent memory (2009, methodology): “However, since DRAM and PCM have similar capacities at the same technology node [1, 9], we expect to have 32 GB PCM DIMMs at the 45 nm node, which is compara-”
• Persistent B+-Trees in Non-Volatile Main Memory (2015, background): “As a result, there are widespread interests in the research community and in the industry to consider incorporating NVM technologies to substitute or complement DRAM as the main memory in future computer systems [5, 9, 36, 15, 26, 7, 31, 8, 33, 29, 20].”
• NOVA: A Log-structured File System for Hybrid Volatile/Non-volatile Main Memories (2016, background): “…technologies Emerging non-volatile memory technologies, such as spin-torque transfer RAM (STT-RAM) [28] [42], phase change memory (PCM) [10] [18] [29] [52], resistive RAM (ReRAM) [22] [62], and 3D XPoint memory technology [1], promise to provide fast, non-volatile, byte-addressable memories .”
• Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling (2009, background): “For example, partial writes [8], li ne evel writeback [15], lazy write [15] and silent store removal [21 ].”
• Approximate storage in solid-state memories (2013, methodology): “PCM and other fast, resistive storage technologies may be used as main memories [21, 36, 47].”
• Phase-Change Memory—Towards a Storage-Class Memory (2017, background): “peripheral circuitry), longer wordline/bitlines are preferred for the memory array, the size of which are limited by the current required to program the memory cell due to IR drop along the wordlines/bitlines [36].”
• Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “A number of Ambit-like bitwise operation substrates have been proposed in recent years, making use of emerging resistive memory technologies, e.g., phasechange memory (PCM) [17, 19, 176, 177, 178, 179], SRAM, or specialized computational DRAM.”
• Energy reduction for STT-RAM using early write termination (2009, methodology): “Since our STT-RAM is at the L2 level, one simple way is to utilize the “dirty” bit in L1 to pass or terminate the writes into the L2, analogous to the write removal technique at the memory level [7].”