Gabriel H. Loh

Hardware and Architecture · 2006–2009

A researcher in the Science corpus: 4 papers; trusts 13 researchers and is trusted by 10 researchers here, as inferred from the citation graph.

Subfields

Hardware and Architecture — 17 citations into it; #412 of 1,551 by trust here, #731 by citations
Computer Networks and Communications — 15 citations into it; #3,184 of 9,886 by trust here, #4,277 by citations
Electrical and Electronic Engineering — 8 citations into it; #7,183 of 16,539 by trust here, #8,176 by citations

Their strongest outbound trust, strongest first, inferred from their citations.

Ordered by how strongly the researchers Gabriel H. Loh trusts endorse each paper. Same corpus, a different order for every researcher.

Fair cache sharing and partitioning in a chip multiprocessor architecture (Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.)
Balancing thoughput and fairness in SMT processors (2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.)
A Case for MLP-Aware Cache Replacement (International Symposium on Computer Architecture)
Dead-block prediction & dead-block correlating prefetchers (Proceedings 28th Annual International Symposium on Computer Architecture)
Temperature-aware microarchitecture (30th Annual International Symposium on Computer Architecture, 2003. Proceedings.)
Drowsy caches: simple techniques for reducing leakage power (Proceedings 29th Annual International Symposium on Computer Architecture)
Adaptive insertion policies for managing shared caches (International Conference on Parallel Architectures and Compilation Techniques)
The microarchitecture of the Pentium 4 processor
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches (Micro)
Die Stacking (3D) Microarchitecture (Micro)