Temperature-aware microarchitecture

By Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan. 30th Annual International Symposium on Computer Architecture, 2003. Proceedings., 2003

1,339 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/b5831b70e060f883e626dacf5a1b008ac7626265

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Citations in the corpus

Compact thermal modeling for temperature-aware design (2004, methodology): “For example, our previous work [5] [6] presents a dynamic compact thermal model, HotSpot , only at the microarchitecture level.”
Live, Runtime Phase Monitoring and Prediction on Real Systems with Application to Dynamic Power Management (2006, background): “Recognizing these phases on-the-fly enables various dynamic optimizations such as hardware reconfigurations, dynamic voltage and frequency scaling (DVFS), thermal management and dynamic hotcode optimizations [1, 4, 5, 7, 11, 15, 25, 28].”
The case for lifetime reliability-aware microprocessors (2004, background): “However, since we do not have the function that relates these constants to cost, we do the following: according to current worst-case based reliability qualiﬁcation methodologies, the architectural parameters in the model equations (temperature ( (cid:0) ), voltage ( (cid:1) ), frequency ( (cid:2)…”
3D-Stacked Memory Architectures for Multi-core Processors (2008, methodology): “We also conduct thermal analysis of 3D-stacked DRAMs using the University of Virginia HotSpot toolset [39].”
HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects (2003, background): “as well as broader processor-design issues like thermal management [4, 17, 25, 26] manipulate parameters like $ and temperature that are hidden in or " # and this makes it more difficult both to reason about these effects (there is an exponential dependence of leakage on $ , for example) and to actu”
Temperature-aware microarchitecture: Modeling and implementation (2004, methodology): “Results with 0.8 K/W are qualitatively similar and have been reported elsewhere [Skadron et al. 2003a, 2003c].”
The impact of technology scaling on lifetime reliability (2004, methodology): “As explained in [14], the RC time constant of the processor heat sink is significantly larger than the RC time constant of individual silicon structures.”
Techniques for Multicore Thermal Management: Classification and New Exploration (2006, methodology): “1063-6897/06 $20.00 (c) 2006 IEEE With temperature control as a key limitation to processor performance, many recent works in computer architecture focus on issues of thermal control [9, 10, 15, 18, 22, 23, 29, 33].”
Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods (2006, methodology): “An architectural thermal model for microprocessor, HotSpot, which constructs a multi-layer lumped thermal RC network, is described in [ 77 ] to model the heat dissipation path from the silicon die through the cooling package to the ambient.”
Temperature and supply Voltage aware performance and power modeling at microarchitecture level (2005, methodology): “HotSpot [18], [19] provides a detailed thermal model based on an equivalent distributed circuit of thermal resistances and capacitances that correspond to microarchitectural units and the package with heat spreader and heatsink.”
Analysis of dynamic voltage/frequency scaling in chip-multiprocessors (2007, methodology): “We use the HotSpot thermal simulation package [11], with our floorplan consisting of a ring of 16 cores around central L2 cache banks.”
Runtime power monitoring in high-end processors: methodology and empirical data (2003, background): “This is particularly true for thermal studies, since it takes a long time for processors to reach equilibrium thermal operating points [24].”
Temperature-Aware Scheduling and Assignment for Hard Real-Time Applications on MPSoCs (2008, methodology): “The X&H heuristic calls HotSpot to compute the temperatures.”
BlueGene/L Failure Analysis and Prediction Models (2006, background): “…hardware device failures are also a growing concern, especially with high power consumption for these large scale systems leading to immense heat dissipation, which in consequence can accelerate the failure rates for different devices [23, 21], including the CPUs, memory systems, and disk drives.”
HotSpot: a compact thermal modeling methodology for early-stage VLSI design (2006, methodology): “7 confirms the accuracy of the above analysis by comparing with FEM simulations using FloWorks.”
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008, methodology): “We use HotSpot [31] to estimate on-chip temperatures.”