A Case for MLP-Aware Cache Replacement

By Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt. International Symposium on Computer Architecture, 2006

337 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/e8b24b543c2434b3fda5da7a92f44e8dea0af8b7

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Citations in the corpus

PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches (2009, methodology): “Both UCP and PIPP make use of shadow tags with dynamic set sampling to track per-core utility curves (32 sets per shadow tag) [33]; both UCP and PIPP use this information to feed to the same partitioning algorithm (optimal for dual-core, and Lookahead [36] for quad-core) to select the target partiti”
A case for exploiting subarray-level parallelism (SALP) in DRAM (2012, background): “, out-of-order execution [60], non-blocking caches [27], fine-grained multithreading [52, 58], runahead execution [5, 39] and other memory-level parallelism mechanisms [4, 45]).”
The evicted-address filter: A unified mechanism to address both cache pollution and thrashing (2012, methodology): “It does so by using set-dueling [35, 36] to determine if a thread incurs fewer misses with the conventional LRU policy or the bimodal insertion policy (BIP).”
Cooperative Caching for Chip Multiprocessors (2006, methodology): “Similarly, processor caches can also exploit the cost difference between misses having non-uniform memory-level parallelism [52], as shown by proposals for cost-sensitive and MLP-aware uniprocessor caches [76, 122].”
Adaptive insertion policies for high performance caching (2007, methodology): “Examples of hybrid replacement schemes include Sampling-Based Adaptive Replacement (SBAR) [13] and Adaptive Cache (AC) [18].”
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches (2006, methodology): “The sampled sets for UMON-DSS are chosen using the simple static policy [12], which means set 0 and every 33rd set is selected.”
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (2008, background): “Parallelism Awareness: The concept of memory-level parallelism awareness was exploited in processor caches to improve the c ac replacement policy [30].”