Adaptive insertion policies for managing shared caches

By Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, J. Sébot, Simon C. Steely Jr., Joel S. Emer. International Conference on Parallel Architectures and Compilation Techniques, 2008

327 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/081dec43c2dbe76ff43c810594495f11ab092a10

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In Computer Networks and Communications

In Hardware and Architecture

Citations in the corpus

MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (2018, background): “Cache insertion policies that account for cache thrashing [55, 56, 108], future reuse [116, 117], or inter-application interference [144] work well for CPU applications, but previous works have shown that some of these policies can be ineffective for GPU applications [16, 74].”
Bubble-up: Increasing utilization in modern warehouse scale computers via sensible co-locations (2011, background): “One direction that has attracted much research attention is the management of shared cache and bandwidth through techniques such as resource partitioning [4, 20, 27–34, 38] , throttling [ 7 ] and adaptive cache replacement policies [ 14 ].”
Cache-Conscious Wavefront Scheduling (2012, background): “Other schemes attempt to manage interference among heterogeneous work-loads [35, 19] but each thread in our workload has roughly similar characteristics.”
Cache Telepathy: Leveraging Shared Resource Attacks to Learn DNN Architectures (2018, background): “Finally, one can add security features to performance-oriented cache partitioning proposals [49],[50],[51],[52], to achieve better trade-offs between security and performance.”
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors (2018, background): “A review [3] of recent cache replacement and protection policies includes valuable commentary on less-cited excellent papers which have left little room for improvement [26, 27, 28, 45, 46, 59].”
SHiP: Signature-based Hit Predictor for high performance caching (2011, result): “This simulation methodology is similar to recent work on shared caches [4, 9, 10, 21, 32].”
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches (2009, background): “multi-core context to reduce the amount of time dead lines take up the valuable shared cache resources [19].”
The evicted-address filter: A unified mechanism to address both cache pollution and thrashing (2012, methodology): “In addition, like TA-DIP, since TA-DRRIP operates at a thread (rather than a block) granularity, it suffers from the short-comings of TA-DIP described before.”
Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation (2011, background): “Many research studies assume a one-IPC model when studying for example memory hierarchy optimizations, the interconnection network and cache coherency protocols in large-scale multiprocessor and multi-core systems [15, 23, 17].”