Die Stacking (3D) Microarchitecture

By Bryan Black, Murali Annavaram, Ned Brekelbaum, J. DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, P. Morrow, Donald W. Nelson, D. Pantuso and 5 more. Micro, 2006

642 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/94e811c11e742e146974581244e00e2f111ccc26

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

Citations in the corpus

RAIDR: Retention-aware intelligent DRAM refresh (2012, methodology): “Furthermore, DRAM integrated in a 3D stack will operate at temperatures over 90 ◦ C [1], leading to reduced retention times (as discussed in Section 3.5) and exacerbating the problems caused by DRAM refresh.”
A durable and energy efficient main memory using phase change memory technology (2009, background): “3D integration provides an opportunity to stack cache or main memory on top of a die that contains multiple processor cores [2, 12, 18, 25].”
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement (2008, background): “With 3D manufacturing becoming mature, 3D architecture exploration attracts substantial number of researchers from industry and academia [1, 5, 6]. Bryan et al. have evaluated the 3D stacking (SRAM Cache or DRAM stack on top of a microprocessor) in terms of power and performance [ 5 ].”
TOP-PIM: throughput-oriented programmable processing in memory (2014, background): “Like other die-stacked designs [12], PIM can run into thermal constraints because in-memory processor and memory share the same path to the heatsink.”
3-D Hyperintegration and Packaging Technologies for Micro-Nano Systems (2009, methodology): “For example, in a 3-D logic-to-logic stack of two strata, scaling to neutral performance yields a 54% power reduction; or frequency and voltage scaling can produce a 34% power reduction with 8% performance improvement; or a simultaneous 15% performance gain and 15% power reduction can be achieved [ ”
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU (2010, background): “Instead, one should explore em rging memory technologies such as 3D-stacking [12] or cache compr ession [5].”
Scaling the bandwidth wall: challenges in and avenues for CMP scaling (2009, methodology): “Another way to increase the effective cache capacity is to implement caches using denser memory such as DRAM [6, 27].”
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (2009, background): “Black, et al . studied the beneﬁts of stacking a large DRAM or SRAM cache on a Intel Core 2 Duo processor, and achieved considerable performanceimprovement[4].”
3D-Stacked Memory Architectures for Multi-core Processors (2008, background): “There are many candidate technologies for 3D die stacking, but wafer-to-wafer bonding appears to be the leading contender in industry [6, 15, 32].”
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, methodology): “Intel is already prototyping an 80-core processor [30, 38] and there is speculation that entire dies in a 3D package may be employed for large SRAM caches or DRAM main memory [7, 23, 30].”
Hybrid cache architecture with disparate memory technologies (2009, background): “Previous work focuses on the performance improvement and power reduction by stacking cache or main memory on top of processors [6, 18, 19, 20].”