3D-Stacked Memory Architectures for Multi-core Processors

By Gabriel H. Loh. International Symposium on Computer Architecture, 2008

698 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/48a7323c4894de3afb90ef2135160205ebb55011

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Citations in the corpus

NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules (2015, background): “The Hybrid Memory Cube (HMC) [71] and 3Dstacking memory and processors [46, 72] promise high memory bandwidth and new opportunities for local data processing.”
A durable and energy efficient main memory using phase change memory technology (2009, background): “3D integration provides an opportunity to stack cache or main memory on top of a die that contains multiple processor cores [2, 12, 18, 25].”
Memory scaling: A systems architecture perspective (2013, background): “, the 3D stacking of memory and logic [46, 2] and increasing cost”
GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks (2017, background): “There have been several prior studies exploiting the technology for die-stacked memory [41]–[45], but beyond that, die-stacking technology can also facilitate implementing the processingin-memory (PIM) concept, which was envisioned decades ago [8]–[11].”
Hybrid cache architecture with disparate memory technologies (2009, background): “[29] Y. Xie, G. H. Loh, B. Black, and K. Bernstein.”
TOP-PIM: throughput-oriented programmable processing in memory (2014, background): “Vertical stacking of logic and memory dies has been widely discussed in the research literature [12, 28, 31, 32].”
Big Data: Astronomical or Genomical? (2015, background): “D memory, integrated computing technologies that overcome the I/O bottle-neck, and networks that are two-to-five orders of magnitude faster because of optical switching [45,46].”
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks (2018, background): “The emergence of 3D-stacked DRAM architectures [71, 75, 90, 94] offers a promising solution.”
A novel architecture of the 3D stacked MRAM L2 cache for CMPs (2009, background): “Loh [22] presented an aggressive 3D DRAM integration as on-chip main memories.”