Balancing thoughput and fairness in SMT processors

By Kun Luo, J. Gummaraju, M. Franklin. 2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS., 2001

319 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture, Information Systems

View Paper: https://www.semanticscholar.org/paper/3ebbddd217946820d8bd593f17dad58dce018620

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Citations in the corpus

Fair cache sharing and partitioning in a chip multiprocessor architecture (2004, background): “Even in SMT architectures, however, the studies have only focused on either improving throughput, or improving throughput without sacrificing fairness too much [8, 17, 15, 12 ].”
Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (2010, unknown): “Metrics: To measure CMP system performance, we use Harmonic mean of Speedups (Hspeedup) [18], and Weighted Speedup (Wspeedup) [28].”
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors (2007, background): “i . This metric should not be used to evaluate system throughput [28, 15 ] since even throughput-oriented realistic systems need to consider fairness and ensure forward progress of individual threads.”
RowClone: Fast and energy-efficient in-DRAM bulk data copy and initialization (2013, unknown): “Harmonic Speedup [35] Improvement 13% 16% 29%”
A case for bufferless routing in on-chip networks (2009, result): “Hmean-Speedup [13], which balances fairness and throughput [33], but since measured hmean- and weighted-speedup results are qualitatively very similar in all our measurements, we mainly pr esent weighted speedups for brevity.”
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems (2008, methodology): “Evaluation Metrics We measure fairness using the unfairness index proposed in [25, together with other threads divided by the memory stall time per instruction it experiences when running alone on the same system: MCPIshared i maxi MemSlowdowni MemSlowdowni = ,Unfairness = MCPIalone minj MemSlowd”
System-Level Performance Metrics for Multiprogram Workloads (2008, methodology): “STP corresponds to the weighted speedup metric proposed by Snavely and Tullsen;(3) and ANTT corresponds to the reciprocal of the hmean metric proposed by Luo, Gummaraju, and Franklin.(4) We provide a system-level meaning for both.”
An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget (2006, background): “Various studies have proposed unified quantitative metrics to incorporate “fairness” into performance gains such as weighted speedup [42] and harmonic mean of thread speedups [ 27 ].”
The evicted-address filter: A unified mechanism to address both cache pollution and thrashing (2012, methodology): “Table 4 shows the percentage improvement of the EAF-cache over the baseline LRU policy and the best previous mechanism, SHIP, on four metrics: weighted speedup [11, 50], instruction throughput, harmonic speedup [28] and maximum slowdown [25, 26].”
ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers (2010, background): “The harmonic speedup of a workload is defined as the harmonic mean of speedups of all comprising threads (higher harmonic-speedup correlates with higher fairness in providing speedup [29]).”
Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (2010, background): “We also report harmonic speedup [8], which measures a balance of fairness and throughput.”
Fair Queuing Memory Systems (2006, methodology): “The performance metric used in Figure 7 is the harmonic mean of the co-scheduled threads’ normalized IPCs [ 13 ].”
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches (2006, background): “The harmonic mean of the normalized IPCs is shown to consider both fairness and performance [9].”
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches (2009, background): “, SMT speedup) Pc i=1 IPC[i]/IPCsa[i], where IPCsa is the stand-alone IPC when the core has exclusive access to the entire processor [31], IPC throughput Pc i=1 IPC[i], and the harmonic mean of weighted speedups c Pc i=1 (IPCsa[i]/IPC[i]) which accounts”
Cooperative Caching for Chip Multiprocessors (2006, background): “For the same reason, two other SMT performance metrics using a single-thread execution baseline—weighted speedup (or WS, which is the sum of speedups) [134] and harmonic mean of speedups [98]—are not used.”