Drowsy caches: simple techniques for reducing leakage power
By K. Flautner, Nam Sung Kim, Steven M. Martin, David T. Blaauw, T. Mudge. Proceedings 29th Annual International Symposium on Computer Architecture, 2002
922 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/93ff2d8b02c7bb57e6289027565332f342879751
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Electrical and Electronic Engineering
- Gabriel H. Loh
- Karthik Sankaranarayanan
- Kevin Skadron
- Mircea R. Stan
- Kaushik Roy
- Luis Ceze
- Adrian Sampson
- Yuan Xie
In Hardware and Architecture
- Gabriel H. Loh
- Karthik Sankaranarayanan
- Kaushik Roy
- Kevin Skadron
- Mircea R. Stan
- Luis Ceze
- Adrian Sampson
- Yuan Xie
Citations in the corpus
- HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects (2003, methodology): “3 Drowsy Caches This method, proposed in [11], utilizes dynamic voltage scaling to reduce the supply voltage of the cell to approximately 1.”
- Microarchitectural techniques for power gating of execution units (2004, background): “Rele et al. [15] use the compiler to identify the onset long idle periods for different functional units, and enable power gating for those units during these idle periods.”
- Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits (2003, methodology): “b) Drowsy cache:Significant leakage reduction can also be achieved by putting the cache into a low-power drowsy mode [79].”
- Hybrid cache architecture with disparate memory technologies (2009, background): “ple yet effective approach is to keep the slow region of a hybrid cache in drowsy mode [12].”
- PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches (2009, background): “Other proposals predict the deadness of a line to save power by either turning off dead lines or putting them into a drowsy state [1, 10, 20].”
- EnerJ: approximate data types for safe and general low-power computation (2011, methodology): “Note that both selective supply voltage for caches [13] and selective refresh rate for DRAM [15] are hardware techniques that have been proposed in the past.”