Processor Design in 3D Die-Stacking Technologies

By Gabriel H. Loh, Yuan Xie, Bryan Black. IEEE Micro, 2007

302 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/c2e1a7a3ba63305b47aad75c293a8ce4f65ebef9

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Gabriel H. Loh
2. Onur Mutlu

In Electrical and Electronic Engineering

1. Erik Jan Marinissen
2. Yervant Zorian
3. Gabriel H. Loh

Citations in the corpus

• Testing 3D chips containing through-silicon vias (2009, background): “TSV-based 3D technologies enable the creation of a new generation of ‘super chips’ by opening up new architectural opportunities [4, 5].”
• 3D-Stacked Memory Architectures for Multi-core Processors (2008, methodology): “Thermocompression is then used to bond the individual layers together to form the 3D stack [27].”