The microarchitecture of the Pentium 4 processor

By G. Hinton, David J. Sager, Mike Upton. 2001

684 citations recorded by the source corpus.

View Paper: https://www.semanticscholar.org/paper/27d913416c4cbdb7a0b9897f4929f823284e9c76

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Citations in the corpus

Managing Wire Delay in Large Chip-Multiprocessor Caches (2004, methodology): “M current prefetchers utilize miss patterns to predict cac misses before they happen [19, 21, 43].”
McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures (2009, unknown): “McPAT can model both a reservation-station model and a physical-register-file model based on real architectures, including the Intel P6 [16] and Netburst [15].”
Processor Design in 3D Die-Stacking Technologies (2007, methodology): “For example, the Intel Pentium 4 20-stage branch misprediction pipeline contains two stages that are just pipelined wires (for example, to drive the branch misprediction signal from the execution units back to the front end).(10) In the subsequent Intel Pentium 4 in 90 nm (Prescott), the branch misp”
ReStore: symptom based soft error detection in microprocessors (2005, background): “Various techniques for doing so exist, some of which are used in today’s microprocessors [5].”
Runahead execution: an alternative to very large instruction windows for out-of-order processors (2003, methodology): “The Retirement RAT [13] contains pointers to those physical registers that contain committed architectural values.”
Adaptive cache compression for high-performance processors (2004, background): “Coupled with the trend toward increasingly deep pipelines [22, 23], main memory latency is expected to grow to hundreds of cycles.”
Transactional lock-free execution of lock-based programs (2002, methodology): “Intel Pentium 4 [70] allow aggressive implementations of memory models by allowing loads to issue speculatively similar to the proposal by Gharachorloo et al.”
Modeling the effect of technology trends on the soft error rate of combinational logic (2002, background): “Five to eight stage pipelines are quite common, and some recent designs use twenty or more stages [11].”
Characterizing the effects of transient faults on a high-performance processor pipeline (2004, background): “Issue 32-entry scheduler w/ speculative wakeup and instruction replay [8]”
Checkpoint processing and recovery: towards scalable large instruction window processors (2003, methodology): “In this scheme, a retirement map table [6] is used in addition to the frontend map table.”
Analyzing CUDA workloads using a detailed GPU simulator (2009, background): “While microprocessors typically employ miss-status holding registers (MSHRs) [21] that use associative comparison logic merge simultaneous requests for the same cache block, the number of outstanding misses that can be supported is typically small (e.g., the original Intel Pentium 4 used four MSHRs ”
Runtime power monitoring in high-end processors: methodology and empirical data (2003, background): “For example, one can consider the four processor subsystems described in [8]: memory, in-order front end, out of order engine, and”