Erik Jan Marinissen
Proceedings International Test Conference 2001 (Cat. No.01CH37260) · 2001–2009
A researcher in the Science corpus: 3 papers; trusts 0 researchers and is trusted by 0 researchers here, as inferred from the citation graph.
Whom Erik Jan Marinissen trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
Papers from Erik Jan Marinissen's perspective
Ordered by how strongly the researchers Erik Jan Marinissen trusts endorse each paper. Same corpus, a different order for every researcher.
- 3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias (International Electron Devices Meeting)
- Processor Design in 3D Die-Stacking Technologies (IEEE Micro)
- 8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology (IEEE Journal of Solid-State Circuits)
- Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs (Proceedings of the IEEE)
- Embedded deterministic test (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)
- 3D silicon integration (Electronic Components and Technology Conference)
- Electrical integrity of state-of-the-art 0.13 /spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication (Digest. International Electron Devices Meeting,)
- Three-dimensional integrated circuits (IBM Journal of Research and Development)
- Influence of cultivation temperature on the ligninolytic activity of selected fungal strains
- Embedded deterministic test for low cost manufacturing test (Proceedings. International Test Conference)
Their papers
- A set of benchmarks for modular testing of SOCs (2002) — 323 citations
- Testing 3D chips containing through-silicon vias (2009) — 323 citations
- Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip (2001) — 411 citations