Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing
By Dieter K. Schroder, J. Babcock. 2003
1,030 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/b63699b255aaa3226becb2180a41aef83c8d477d
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In Electrical and Electronic Engineering
- Tibor Grasser
- Souvik Mahapatra
- Hans Reisinger
- M. A. Alam
- Wenping Wang
- Haldun Kufluoglu
- Thomas Aichinger
- Dhanoop Varghese
Citations in the corpus
- The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps (2011, background): “unanimously supportive of this reaction–diffusion (RD) theory until about 2006 [2]–[5].”
- Investigation and modeling of interface and bulk trap generation during negative bias temperature instability of p-MOSFETs (2004, neutral): “analog CMOS circuits [3]–[21].”
- The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis (2010, background): “speed or in extreme cases to a functional failure [6], [7].”
- Modeling and minimization of PMOS NBTI effect for robust nanometer design (2006, neutral): “Keywords: NBTI, Reliability, Threshold Voltage, Temperature, Performance Degradation, Variability.”
- Impact of NBTI on the temporal performance degradation of digital circuits (2005, background): “Due to NBTI, the threshold voltage of the transistor increases with time resulting in the reduction in drive current [3], which in turn results in temporal performance degradation of circuits.”
- A comprehensive model of PMOS NBTI degradation (2005, neutral): “2004 Published by Elsevier Ltd.”
- A comprehensive model for PMOS NBTI degradation: Recent progress (2007, background): “The exponent n = 1/6 reflects the bottleneck of H–H2 conversion which results in higher H concentration at the Si/ SiO2 interface [3].”
- Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology (2007, background): “It manifests itself as an increase in the threshold voltage Vth of the PMOS transistor [4], [7], [16], [25], [29].”