Universal recovery behavior of negative bias temperature instability [PMOSFETs]

By S. Rangan, N. Mielke, E.C.C. Yeh. IEEE International Electron Devices Meeting 2003, 2003

299 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/78ba724558080a970e7cd842f6db0797d56f442d

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In Electrical and Electronic Engineering

Citations in the corpus

RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance (2009, background): “These uncertainties can be attributed to worsening inter- and intra-die process variations, temperature hotspots, supply voltage fluctuations, signal integrity concerns and aging effects such as Time Dependent Dielectric Breakdown [9] and Negative Bias Temperature Instability [8].”
On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy? (2007, methodology): “1), delay IDLIN shows higher n compared to on-the-fly IDLIN due to recovery [3],[4],[7].”
Recent Issues in Negative-Bias Temperature Instability: Initial Degradation, Field Dependence of Interface Trap Generation, Hole Trapping Effects, and Relaxation (2007, background): “As one may suspect, such an assumption of instantaneous dimerization would not be appropriate to interpret very short term NBTI data.”
The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps (2011, background): “[72], who showed a strong recovery of ΔICP.”
Impact of NBTI on SRAM read stability and design for reliability (2006, background): “also accompanied by a process of annealing of these traps when the negative bias applied at the gate is removed [4], [6] , [9], [14], [16]–[19], [22], [23].”
A Comparative Study of Different Physics-Based NBTI Models (2013, methodology): “method), to obtain degradation of device parameters such as ΔVT [2]–[4], [15], Δgm [2], ΔS [3], and ΔIDLIN and ΔIDSAT [15]; it is now well known that this approach suffers from recovery-related artifacts [24] due to large measurement (stress-off) time (approximately few seconds) and is now seldom us”
Analysis of NBTI Degradation- and Recovery-Behavior Based on Ultra Fast VT-Measurements (2006, result): “This gate voltage VT can be recorded after the settling time of the feedback loop about 1μs after stress – roughly a factor of 1000 faster than in previous studies [11].”
On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress (2006, background): “following; 1) a mix of H2 and H species; 2) H species plus dispersive transport; and 3) H2 species plus recovery due to measurement delay [14], [15].”