DRAMSim2: A Cycle Accurate Memory System Simulator

By Paul Rosenfeld, Elliott Cooper-Balis, Bruce L. Jacob. IEEE computer architecture letters, 2011

910 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/e35328307e83f5a6c3dcf36474862863b7014fb3

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Citations in the corpus

Ramulator: A Fast and Extensible DRAM Simulator (2016, background): “example, two of the most popular simulators (DRAMSim2 [25] and”
Big/little deep neural network for ultra low power inference (2015, methodology): “[31] P. Rosenfeld et al., DRAMSim2: A cycle accurate memory system simulator, IEEE Computer Architecture Letters, 10(1):16-19, 2011.”
Graphicionado: A high-performance and energy-efficient accelerator for graph analytics (2016, methodology): “It is also integrated with the open-source DRAM simulator DRAMSim2 [41] to simulate the cycle-accurate behavior of the off-chip memory accesses.”
GOBO: Quantizing Attention-Based NLP Models for Low Latency and Energy Efficient Inference (2020, methodology): “Cycle times are measured using a custom cycle-accurate simulator which uses DRAMsim2 [33] to model off-chip transfers for a DDR4-3200 dual-channel DRAM main memory.”
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning (2018, background): “, by integration with DRAMSim2 [40], its latency/energy will be the dominant factor from the whole system point of view.”
Tiered-latency DRAM: A low latency and low cost DRAM architecture (2013, methodology): “We developed a cycle-accurate DDR3-SDRAM simulator that we validated against Micron’s Verilog behavioral model [28] and DRAMSim2 [42].”
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating (2019, methodology): “In this performance model, we first extract the memory trace and the compute time of an accelerator from a cycle-accurate RTL simulation, use DRAMSim2 [29] for DRAM latency estimates for memory accesses, and combine the results to obtain the overall execution time.”
RAIDR: Retention-aware intelligent DRAM refresh (2012, methodology): “To evaluate our mechanism, we use an in-house x86 simulator with a cycle-accurate DRAM timing model validated against DRAMsim2 [42], driven by a frontend based on Pin [27].”
A case for exploiting subarray-level parallelism (SALP) in DRAM (2012, methodology): “We developed a cycle-accurate DDR3-SDRAM simulator that we validated against Micron’s Verilog behavioral model [34] and DRAMSim2 [48].”
DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator (2020, positive): “To address these issues, we developed DRAMsim3, a successor to DRAMSim2 [14].”
GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks (2017, methodology): “We extend VaultSim with extra timing models based on DRAMSim2 [30].”
The gem5 Simulator: Version 20.0+ (2020, methodology): “DRAM-Sim [46, 62, 73] which provides a cycle-accurate DRAM models has also been integrated with gem5.”