RAIDR: Retention-aware intelligent DRAM refresh

By Jamie Liu, Ben Jaiyen, Richard Michael Veras, Onur Mutlu. International Symposium on Computer Architecture, 2012

545 citations recorded by the source corpus.

Dynamic random-access memory (DRAM) is the building block of modern main memory systems. DRAM cells must be periodically refreshed to prevent loss of data. These refresh operations waste energy and degrade system performance by interfering with memory accesses. The negative effects of DRAM refresh increase as DRAM device capacity increases. Existing DRAM devices refresh all cells at a rate determined by the leakiest cell in the device. However, most DRAM cells can retain data for significantly longer. Therefore, many of these refreshes are unnecessary. In this paper, we propose RAIDR (Retention-Aware Intelligent DRAM Refresh), a low-cost mechanism that can identify and skip unnecessary refreshes using knowledge of cell retention times. Our key idea is to group DRAM rows into retention time bins and apply a different refresh rate to each bin. As a result, rows containing leaky cells are refreshed as frequently as normal, while most rows are refreshed less frequently. RAIDR uses Bloom filters to efficiently implement retention time bins. RAIDR requires no modification to DRAM and minimal modification to the memory controller. In an 8-core system with 32 GB DRAM, RAIDR achieves a 74.6% refresh reduction, an average DRAM power reduction of 16.1%, and an average system performance improvement of 8.6% over existing systems, at a modest storage overhead of 1.25 KB in the memory controller. RAIDR's benefits are robust to variation in DRAM system configuration, and increase as memory capacity increases.

Subfields: Computer Networks and Communications, Hardware and Architecture, Information Systems

View Paper: https://www.semanticscholar.org/paper/2913004da8f897d20f31c047b46c8cfdcd0eb7d3

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Citations in the corpus

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery (2015, background): “take advantage of these characteristics [37][38][40][41][42], retention charac-”
RowHammer: A Retrospective (2019, background): “, [56], [57], [59], [97], [112]–[116], [124]–[126], [128], [132], [145]–[147], [149], [158], [159], [163], [173], [181], [201], [203], [215]–[217], [229]–[231], [235], [236], and [250]).”
Memory scaling: A systems architecture perspective (2013, methodology): “Several key issues to tackle include: 1) reducing the negative impact of refresh on energy, performance, QoS, and density scaling [45], 2) improving DRAM parallelism/bandwidth [34], latency [42], and energy efficiency [34, 42, 45], 3) improving reliability of DRAM cells at low cost, 4) reducing the ”
Processing Data Where It Makes Sense: Enabling In-Memory Computation (2019, background): “It is well known that the retention time of different cells in DRAM are widely different due to process manufacturing variation [14, 101].”
Overcoming the challenges of crossbar resistive memory architectures (2015, background): “Researchers have been exploring novel architectures around this idea such as a flat hierarchy with combined memory and storage [38], and byte addressable persistent memory for high performance [7].”
Evaluating STT-RAM as an energy-efficient main memory alternative (2013, methodology): “For a detailed description of DRAM refresh, we refer the reader to [36].”
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors (2014, methodology): “Depending on the implementation, some cells represent a logical value of ‘1’ using the charged state, while other cells do so using the discharged state — these cells are referred to as true-cells and anti-cells, respectively [44].”
Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology (2017, background): “Second, each copy operation refreshes the cells of the destination row by accessing the row [78].”
TRRespass: Exploiting the Many Sides of Target Row Refresh (2020, methodology): “Thus, the memory controller needs to refresh the contents of all cells periodically (usually every 64ms [40], [44], [67]) to prevent data loss.”
Ramulator: A Fast and Extensible DRAM Simulator (2016, unknown): “Academic SBA/SSA (2010) [38]; Staged Reads (2012) [8]; RAIDR (2012) [27]; SALP (2012) [24]; TL-DRAM (2013) [26]; RowClone (2013) [37]; Half-DRAM (2014) [39]; Row-Buffer Decoupling (2014) [33]; SARP (2014) [6]; AL-DRAM (2015) [25]”