David T. Blaauw
Electrical and Electronic Engineering · 2000–2018
A researcher in the Science corpus: 19 papers; trusts 2 researchers and is trusted by 1 researcher here, as inferred from the citation graph.
Subfields
- Electrical and Electronic Engineering — 47 citations into it; #15,814 of 16,539 by trust here, #4,881 by citations
- Hardware and Architecture — 34 citations into it
Whom David T. Blaauw trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
Who trusts David T. Blaauw overall
Papers from David T. Blaauw's perspective
Ordered by how strongly the researchers David T. Blaauw trusts endorse each paper. Same corpus, a different order for every researcher.
- Automatically characterizing large scale program behavior (ASPLOS X)
- Theoretical and practical limits of dynamic voltage scaling (Proceedings - Design Automation Conference)
- Razor: a low-power pipeline based on circuit-level timing speculation
- Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
- Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage (2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315))
- The gem5 simulator (CARN)
- Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories (International Symposium on Low Power Electronics and Design)
- A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets
- DoReFa-Net: Training Low Bitwidth Convolutional Neural Networks with Low Bitwidth Gradients
- A and V
Their papers
- Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks (2018) — 392 citations
- Drowsy caches: simple techniques for reducing leakage power (2002) — 922 citations
- Razor: a low-power pipeline based on circuit-level timing speculation (2003) — 1,460 citations
- Theoretical and practical limits of dynamic voltage scaling (2004) — 445 citations
- 14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence (2017) — 79 citations
- A self-tuning DVS processor using delay-error detection and correction (2005) — 445 citations
- Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits (2010) — 884 citations
- RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance (2009) — 603 citations
- A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory (2016) — 318 citations
- Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance (2008) — 397 citations
- Leakage Current: Moore's Law Meets Static Power (2003) — 1,329 citations
- OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator (2018) — 319 citations
- Compute Caches (2017) — 331 citations
- A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V (2012) — 402 citations
- A cubic-millimeter energy-autonomous wireless intraocular pressure monitor (2011) — 320 citations
- Statistical Timing Analysis: From Basic Principles to State of the Art (2008) — 391 citations
- Statistical timing analysis for intra-die process variations with spatial correlations (2003) — 481 citations
- Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads (2002) — 496 citations
- Hierarchical analysis of power distribution networks (2000) — 340 citations