A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets

By Bert Moons, Marian Verhelst. 2016

155 citations recorded by the source corpus.

A low-power precision-scalable processor for ConvNets or convolutional neural networks (CNN) is implemented in a 40nm technology. Its 256 parallel processing units achieve a peak 102GOPS running at 204MHz. To minimize energy consumption while maintaining throughput, this works is the first to both exploit the sparsity of convolutions and to implement dynamic precision-scalability enabling supply- and energy scaling. The processor is fully C-programmable, consumes 25-288mW at 204 MHz and scales efficiency from 0.3-2.6 real TOPS/W. This system hereby outperforms the state-of-the-art up to 3.9× in energy efficiency.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering

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Citations in the corpus

Deep Learning for IoT Big Data and Streaming Analytics: A Survey (2017, background): “[156] also developed a tiny processor for CNNs (total active area of 1.”
14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOI (2017, methodology): “State-of-the-art ASICs in references [3] and [4] only show 1.”
Cognitive computation and communication: A complement solution to cloud for IoT (2016, methodology): “The low power CNN processor from [39] expands on methods of data locality and guarding memory”
14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence (2017, background): “Off-chip weight storage in DRAM is also common in the prior works [2-3], which implies significant additional power consumption due to intensive off-chip data movement.”
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Network (2017, background): “propose aggressive voltage scaling techniques at low precision for increased energy efficiency at constant throughput by turning off parts of the multiplier [37, 52].”
Artificial optic-neural synapse for colored and color-mixed pattern recognition (2018, methodology): “Additionally, to con ﬁ rm if this synaptic device can achieve the number of conductance states that were typically demanded for inference of DNNs (6 − 8 bits = 64 − 256 states) 32,33 , we applied excitatory and inhibitory pulses 600 times each (see Fig.”
Efficient Acceleration of Deep Learning Inference on Resource-Constrained Edge Devices: A Review (2023, methodology): “AlexNet can be quantized using a variable precision of 4 to 9 bits with less than 1% accuracy degradation [119].”
14.4 A scalable speech recognizer with deep-neural-network acoustic models and voice-activated power gating (2017, background): “[2]) targets convolutional networks (CNNs) for computer vision applications.”