Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
By J. Tschanz, J. Kao, S. Narendra, R. Nair, D. Antoniadis, Anantha P. Chandrakasan, V. De. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002
791 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/99fd99b9aac50e5fda7fe47c2fd4ac2c764bc0c5
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Citations in the corpus
- Statistical Timing Analysis: From Basic Principles to State of the Art (2008, methodology): “One approach to address this inefficiency is to use runtime adaptivity of the design [6], [7].”
- 0.5-V analog circuit techniques and their application in OTA and filter design (2005, methodology): “In [7], [8], [19], and [20], adaptive body bias techniques have been used to optimize the delay through critical paths in digital circuits.”
- Parameter variations and impact on circuits and microarchitecture (2003, methodology): “A testchip (Fig. 15) has been implemented in a 150nm CMOS technology to evaluate effectiveness of the adaptive body bias (ABB) technique [ 10 ] for minimizing impacts of both die-to-die and within-die parameter variations on processor frequency and active leakage power.”