A self-tuning DVS processor using delay-error detection and correction
By Shidhartha Das, D. Roberts, Seokwoo Lee, Sanjay Pant, David T. Blaauw, Todd M. Austin, K. Flautner, T. Mudge. IEEE Journal of Solid-State Circuits, 2005
445 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering
View Paper: https://www.semanticscholar.org/paper/03039c4fac55e55a9592e8718189249ce49a3a95
How researchers see this paper
The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.
In Electrical and Electronic Engineering
- Gu-Yeon Wei
- David M. Brooks
- José Miguel Hernández-Lobato
- Nam Sung Kim
- David T. Blaauw
- Josep Torrellas
- Sanjay Pant
- Shidhartha Das
Citations in the corpus
- VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects (2008, background): “[27], who reduce the supply voltage of the logic units in an Alpha-like pipeline and measure the error rate in errors per cycle.”
- Statistical Timing Analysis: From Basic Principles to State of the Art (2008, methodology): “One approach to address this inefficiency is to use runtime adaptivity of the design [6], [7].”
- Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance (2009, methodology): “In Section II, EDS circuits for dynamic variation tolerance are reviewed and two EDS circuits [10] are introduced to retain the error-detection capability in previous work [5]–[9] while lowering clock energy and eliminating datapath metastability.”
- Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance (2008, methodology): “Hence the energy gain from operating substantially below the PoFF is small (~10%) compared to the energy gain from eliminating the PVT margins (~35 to 45%) [5].”
- RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance (2009, methodology): “Hence the energy gain from operating substantially below the PoFF was small ( 10%) compared to the energy gain from eliminating the PVT margins ( 35 to 45%) [5].”
- Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators (2016, methodology): “A number of techniques have been described to detect faults arising from voltage scaling, including parity bits [36], Razor double-sampling [37, 38], Razor transitiondetection [39], and various canary circuits [40].”