Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance
By David T. Blaauw, Sudherssen Kalaiselvan, Kevin Lai, Wei-Hsiang Ma, Sanjay Pant, Carlos Tokunaga, Shidhartha Das, David M. Bull. IEEE International Solid-State Circuits Conference, 2008
397 citations recorded by the source corpus.
Subfields: Electrical and Electronic Engineering, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/0141db2ddce32ce5fe5cac429413f44755cb309e
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In Electrical and Electronic Engineering
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Citations in the corpus
- Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance (2009, methodology): “In comparing TDTB and DSTB across a variety of known EDS circuit options, including Razor II [17], TDTB appears to be the lowest clock energy EDS circuit; DSTB appears to be the lowest clock energy static-EDS circuit with SER protection [10].”