Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories

By Michael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar. International Symposium on Low Power Electronics and Design, 2000

875 citations recorded by the source corpus.

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both <italic>within</italic> and <italic>across</italic> appliðcations. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy dissipation in instrucðtion caches. We propose, <italic>gated-V<subscrpt>dd</subscrpt>,</italic> a circuit-level technique to gate the supply voltage and reduce leakage in unused SRAM cells. Our results indicate that gated-V<subscrpt>dd</subscrpt> together with a novel resizable cache architecture reduces energy-delay by 62% with minimal impact on performance.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/91a6e8ae9c5fb90423e8d4ae216bd45807d44047

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Citations in the corpus

Microarchitectural techniques for power gating of execution units (2004, background): “Prior circuit-level approaches to leakage power reduction include: body-bias control [4], dual-threshold domino circuits [10], input vector control [9] and power-gating [14].”
A highly configurable cache architecture for embedded systems (2003, methodology): “Since we instead use way concatenation to reduce dynamic power and since we want to use way shutdown to reduce static power, we use the shutdown method by Powell [20], involving a circuit level technique called gated-Vdd, shown in Figure 9.”
An Adaptive Issue Queue for Reduced Power at High Performance (2000, result): “Therefore, downsizing to a smaller number of entries results in a faster issue queue cycle time and saves energy, similar to prior work related to adaptive cache designs [11, 12, 13].”
HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects (2003, methodology): “Recently, a great deal of research work in the architecture community has focused on reducing leakage power in the caches [11, 13, 14, 18, 22 , 27, 28], branch predictor [15, 16], register file [2], issue queues [12, 21, 8, 9], and the ALUs [10].”
Drowsy caches: simple techniques for reducing leakage power (2002, methodology): “Approaches for reducing static power consumption of caches by turning off cache lines using the gated-VoD technique [ 1 ] have been described in [2][3].”
A brief survey on power gating design (2010, methodology): “Firstly, two extreme implementation styles were proposed, the cell-based design[12] and the module-based design[13].”