RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance

By Shidhartha Das, Carlos Tokunaga, Sanjay Pant, Wei-Hsiang Ma, Sudherssen Kalaiselvan, Kevin Lai, David M. Bull, David T. Blaauw. IEEE Journal of Solid-State Circuits, 2009

603 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/66dfc8e4bdbc0951ede5172359fe1c6d7990465c

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In Electrical and Electronic Engineering

1. Gu-Yeon Wei
2. David M. Brooks
3. José Miguel Hernández-Lobato
4. Massimo Alioto
5. Brandon Reagen
6. Carole-Jean Wu

Citations in the corpus

• Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial (2012, background): “, Razor I [75], Razor II [76], TBTD and DSTB [77]).”
• Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators (2016, methodology): “In fault-tolerant CPU applications a typical correction mechanism is to recompute using checkpoint and replay [39, 41, 42], a capability specific to the sophisticated control-plane logic of”