Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

By Yu-hsin Chen, Tushar Krishna, Joel S. Emer, Vivienne Sze. 2016

2,806 citations recorded by the source corpus.

Subfields: Computer Vision and Pattern Recognition, Electrical and Electronic Engineering, Efficiency & Compression, ML Systems & Hardware

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Citations in the corpus

Deep Learning for IoT Big Data and Streaming Analytics: A Survey (2017, background): “3) Accelerators: Designing specific hardware and circuits is another active research direction aiming to optimize the energy efficiency [191] and memory footprint [192] of DL”
NetAdapt: Platform-Aware Neural Network Adaptation for Mobile Applications (2018, methodology): “However, this requires designing models to estimate the direct metrics of each target platform, which requires detailed knowledge of the platform including its hardware architecture [3], and the network-to-array mapping used in the toolchain [2].”
Designing Energy-Efficient Convolutional Neural Networks Using Energy-Aware Pruning (2016, methodology): “The hardware parameters used are similar to [22].”
SqueezeNext: Hardware-Aware Neural Network Design (2018, methodology): “Eyeriss [3] introduced a taxonomy for classifying neural network accelerators based on the spatial architecture according to the type of the data to be reused at the lowest level of the memory hierarchy.”
Training and Inference with Integers in Deep Neural Networks (2018, background): “, 2016), as well as dedicated hardware for commercial solutions (Jouppi et al., 2017; Chen et al., 2017; Shi et al., 2015).”
Designing Adaptive Neural Networks for Energy-Constrained Image Classification (2018, neutral): “, hardware accelerators [4]).”
Deep Supervised Learning Using Local Errors (2017, background): “…accelerators developed to accelerate just the inference (feedforward) phase (Himavathi et al., 2007; Cavigelli et al., 2015; Ardakani et al., 2017; Chen et al., 2016; Han et al., 2016; Aimar et al., 2017; Jouppi et al., 2017), where a complete forward pass through a large-scale convolutional…”
CaffePresso: An optimized library for Deep Learning on embedded accelerator-based platforms (2016, background): “While there is significant interest in design of ASICs customized for deep learning [5, 8, 6, 2, 3], along with large FPGA-based [10, 14, 7] and GPU-based accelerators [13] for high-performance systems, we investigate the potential of commercial off-the-shelf SoC hardware for efficiently implementin”
ApproxDBN: Approximate Computing for Discriminative Deep Belief Networks (2017, background): “The majority of hardware neural network implementations have been done for feedforward deterministic networks [4][7].”
Compact and Computationally Efficient Representation of Deep Neural Networks (2018, neutral): “Note that similar energy models have been previously proposed [50], [51].”
Survey of Machine Learning Accelerators (2020, background): “• MIT Eyeriss chip 〈Eyeriss〉 [12], [37], [38] is a research chip from Vivienne Sze’s group in MIT CSAIL.”
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory (2017, methodology): “The area and power consumption of each PE are scaled from [8, 12], assuming 0.”
Toward Massive Machine Type Communications in Ultra-Dense Cellular IoT Networks: Current Issues and Machine Learning-Assisted Solutions (2018, background): “ticular accelerators in the form of hardware and circuits with the objective of optimizing memory footprint [39] and energy efficiency [40] of DL models.”
From high-level deep neural models to FPGAs (2016, methodology): “[23, 43] develop an ASIC design with a 2D spatial array of PEs for Convolutional Neural Networks.”
Pre-Defined Sparsity for Low-Complexity Convolutional Neural Networks (2020, methodology): “In particular, as implemented in Eyeriss [13], at 62% density, RLC would lead to 0.”
PredictiveNet: An energy-efficient convolutional neural network via zero prediction (2017, methodology): “Although CNNs have provided an efficient method to constrain its complexity by weight sharing and restricting to local connections, the required amount of computation is still large, with convolutional operations usually taking up over 90% of the total computational power [4].”