Sanjay Pant
Electrical and Electronic Engineering · 2003–2009
A researcher in the Science corpus: 4 papers; trusts 1 researcher and is trusted by 0 researchers here, as inferred from the citation graph.
Subfields
- Electrical and Electronic Engineering — 9 citations into it
Whom Sanjay Pant trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
Who trusts Sanjay Pant overall
Papers from Sanjay Pant's perspective
Ordered by how strongly the researchers Sanjay Pant trusts endorse each paper. Same corpus, a different order for every researcher.
- Automatically characterizing large scale program behavior (ASPLOS X)
- Theoretical and practical limits of dynamic voltage scaling (Proceedings - Design Automation Conference)
- Razor: a low-power pipeline based on circuit-level timing speculation
- A self-tuning DVS processor using delay-error detection and correction (IEEE Journal of Solid-State Circuits)
- Computer Architecture: A Quantitative Approach
- Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories (International Symposium on Low Power Electronics and Design)
- The gem5 simulator (CARN)
- Design issues for Dynamic Voltage Scaling (ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514))
- Design of High-Performance Microprocessor Circuits
- Gradient-based learning applied to document recognition
Their papers
- Razor: a low-power pipeline based on circuit-level timing speculation (2003) — 1,460 citations
- A self-tuning DVS processor using delay-error detection and correction (2005) — 445 citations
- RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance (2009) — 603 citations
- Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance (2008) — 397 citations