OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator
By S. Pal, Jonathan Beaumont, Dong-hyeon Park, Aporva Amarnath, Siying Feng, C. Chakrabarti, Hun-Seok Kim, David T. Blaauw, T. Mudge, Ronald Dreslinski Jr.. International Symposium on High-Performance Computer Architecture, 2018
319 citations recorded by the source corpus.
Subfields: Computer Networks and Communications, Computer Vision and Pattern Recognition, Hardware and Architecture
View Paper: https://www.semanticscholar.org/paper/061edcbe54d23e6c8688525503ebc643c30d44a0
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In Computer Networks and Communications
In Computer Vision and Pattern Recognition
In Hardware and Architecture
Citations in the corpus
- AWB-GCN: A Graph Convolutional Network Accelerator with Runtime Workload Rebalancing (2019, unknown): “Pal [54] proposes an outer-product-based SpMM architecture.”
- SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning (2020, background): “However, it is not friendly to CPUs and GPUs and requires dedicated hardware [23], [24] to support sparse matrix multiplication, which may consume extra efforts for design”
- SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training (2020, methodology): “We compare SIGMA against other state-of-the-art accelerators: TPU [4], EIE [19], SCNN [33], OuterSPACE [32], Eyeriss v2 [11], Packed Systolic [26], and Cambricon-X [47].”