A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory

By Supreet Jeloka, Naveen Akesh, D. Sylvester, David T. Blaauw. IEEE Journal of Solid-State Circuits, 2016

318 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/67b76200ca430d3dc7b980f9a6570eb2cd188c06

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Abu Sebastian
2. M. Le Gallo
3. Evangelos Eleftheriou
4. David T. Blaauw
5. Luca Benini

In Hardware and Architecture

1. R. Iyer
2. Abu Sebastian
3. David T. Blaauw
4. M. Le Gallo

Citations in the corpus

• Memory devices and applications for in-memory computing (2020, background): “NaTuRe NaNoTecHNology This non-volatile accumulative behaviour, in spite of its nonlinear and stochastic nature, can be exploited in several applications, such as training deep neural networks, where the conductance values need to be incrementally modified.”
• Compute Caches (2017, methodology): “Further, these estimates are conservative when compared to measurements on silicon [2] in order to provision for robust margin against”
• Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks (2018, background): “chip implementation [8] and architectural prototype [9] that shows how simple logic operations (AND/NOR) can be”