Razor: a low-power pipeline based on circuit-level timing speculation

By Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, C. Ziesler, David T. Blaauw, Todd M. Austin, K. Flautner and 1 more. 2003

1,460 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture, ML Systems & Hardware

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Electrical and Electronic Engineering

1. Sparsh Mittal
2. Luis Ceze
3. Adrian Sampson
4. Nam Sung Kim
5. Michael Nicolaidis
6. Doug Burger
7. Subhasish G. Mitra
8. David T. Blaauw

In Hardware and Architecture

1. Luis Ceze
2. Adrian Sampson
3. Sparsh Mittal
4. Nam Sung Kim
5. Michael Nicolaidis
6. Hadi Esmaeilzadeh
7. Doug Burger
8. Subhasish G. Mitra

In ML Systems & Hardware

1. Subhasish G. Mitra
2. Nam Sung Kim
3. Hadi Esmaeilzadeh
4. Luis Ceze
5. Sparsh Mittal

Citations in the corpus

• EnerJ: approximate data types for safe and general low-power computation (2011, background): “Aggressive voltage scaling can result in over 30% energy reduction with ∼ 1% error rate [10] and 22% reduction with ∼ 0.”
• VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects (2008, methodology): “net-level data for the microprocessor, the critical path distribution of each logic stage is assumed to match that of the multiplier in [25].”
• Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors (2008, neutral): “[7], who characterized a multiplier unit.”
• RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance (2009, methodology): “voltage management technique, for Dynamic Voltage Scaled (DVS) processors, based on in situ error detection and correction, called Razor [13].”
• Design for soft error mitigation (2005, background): “Recently, [51] and [52] proposed to reduce the power dissipation of a circuit by reducing the power supply at a level lower than the one required to guarantee correct operation under worst-case conditions.”
• Circuit Failure Prediction and Its Application to Transistor Aging (2007, methodology): “Our circuit failure prediction technique complements timing error detection techniques such as [Ernst 03, Franco 94, Nicolaidis 99].”
• Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance (2009, methodology): “In the 3-stage pipeline circuit block, error signals from each EDS circuit per pipeline stage are combined via an OR tree to generate a single error signal (FINAL ERROR) [8], [9].”
• Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance (2008, methodology): “voltage management technique, for Dynamic Voltage Scaled (DVS) processors, based on in situ error detection and correction, called Razor [13].”
• Architecture support for disciplined approximate programming (2012, methodology): “dd L and employs error correction to guarantee correct behavior using an approach similar to Razor [10].”