Speculative lock elision: enabling highly concurrent multithreaded execution

By Ravi Rajwar, James R. Goodman. Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture. MICRO-34, 2001

515 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/1d8adf1dcfb16411bc3a36f8f374ef78d964c258

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Håkan Grahn
2. T. Harris
3. Keir Fraser
4. Onur Mutlu
5. J. Larus
6. Ravi Rajwar
7. Moinuddin K. Qureshi
8. Yale N. Patt

In Electrical and Electronic Engineering

1. Håkan Grahn
2. T. Harris
3. Keir Fraser
4. J. Larus
5. Andrew Waterman
6. David A. Patterson
7. Yunsup Lee
8. K. Asanovi

In Hardware and Architecture

1. Håkan Grahn
2. T. Harris
3. Keir Fraser
4. Onur Mutlu
5. J. Larus
6. Ravi Rajwar
7. Moinuddin K. Qureshi
8. Yale N. Patt

Citations in the corpus

• Transactional memory (2010, methodology): “TLR uses Speculative Lock Elision (SLE) [77] as an enabling mechanism in order to create an optimistic transaction.”
• The RISC-V Instruction Set Manual (2014, methodology): “We recommend the use of AMOs for both lock acquire and release to simplify the implementation of speculative lock elision [18].”
• Accelerating critical section execution with asymmetric multi-core architectures (2009, background): “TLR improves upon SLE by pro­viding a timestamp-based con.ict resolution scheme that en­ables lock-free execution.”
• Unbounded transactional memory (2005, background): “Of particular relevance to our work are Speculative Lock Elision (SLE) [31] and Transactional Lock Removal (TLR) [32], which speculatively identify locks and use the cache to give the appearance of atomicity.”
• GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks (2017, background): “There have been multiple research efforts to reduce the overhead of locks and critical sections by accelerating critical sections [49] or by using Speculative Lock Elision (SLE) [50] and Transactional Memory [51].”
• Concurrent programming without locks (2007, methodology): “Rajwar and Goodman have subsequently suggested similar techniques for speculatively executing lock-based code [ Rajwar and Goodman 2002; 2001 ].”
• Transactional Memory, 2nd edition (2010, methodology): “Examples of implicit HTM systems include Speculative Lock Elision [248], the Rock HTM [82], and the Azul HTM mechanisms [66].”
• The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0 (2014, unknown): “We recommend the use of AMOs for both lock acquire and release to simplify the implementation of speculative lock elision [18].”
• Virtualizing transactional memory (2005, unknown): “Speculative Lock Elision [19] and Transactional Lock Removal [20] are hardware proposals that take existing lock-based programs, and execute them in a lock-free manner to attain transactional behavior.”
• Transactional lock-free execution of lock-based programs (2002, background): “Speculative Lock Elision [30] dynami- cally elides lock acquire and release operations from an execution stream but requires lock acquisitions in the presence of conflicts.”
• Hybrid transactional memory (2006, background): “Related techniques have been proposed for ensuring atomicity of critical sections without acquiring their locks [26], and for speculating past other synchronization constructs [18].”