Accelerating critical section execution with asymmetric multi-core architectures

By M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt. International Conference on Architectural Support for Programming Languages and Operating Systems, 2009

320 citations recorded by the source corpus.

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Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior (2010, background): “In contrast, the execution time of the second type of multithreaded applications is determined by slow-running critical threads [22, 1, 2].”
GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks (2017, background): “There have been multiple research efforts to reduce the overhead of locks and critical sections by accelerating critical sections [49] or by using Speculative Lock Elision (SLE) [50] and Transactional Memory [51].”
Memory scaling: A systems architecture perspective (2013, background): “More and increasingly heterogeneous [15, 70, 29] processing cores and agents/clients are sharing the memory system, leading to increasing demand for memory capacity and bandwidth along with a relatively new demand for predictable performance and QoS from the memory system [52, 57, 69].”
A scalable processing-in-memory accelerator for parallel graph processing (2015, methodology): “For simplicity and generality, we implement computation movement as a remote function call [4, 57].”