Checkpoint processing and recovery: towards scalable large instruction window processors

By Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan. Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36., 2003

321 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/f0c9fc3a05547d2603b6216dda9e153669f48aba

How researchers see this paper

The researchers whose trusted networks rank it highest, strongest advocate first. Every researcher gets a different order.

In Computer Networks and Communications

1. Onur Mutlu
2. Moinuddin K. Qureshi
3. Yale N. Patt
4. Nicholas J. Wang
5. Daniel N. Lynch
6. Sanjay J. Patel
7. Gabriel H. Loh
8. Yuejian Xie

In Hardware and Architecture

1. Onur Mutlu
2. Moinuddin K. Qureshi
3. Yale N. Patt
4. Nicholas J. Wang
5. Sanjay J. Patel
6. Daniel N. Lynch
7. Gabriel H. Loh
8. Yoongu Kim

Citations in the corpus

• A Case for MLP-Aware Cache Replacement (2006, background): “Several proposals [15][1][4][25] have looked at the problem of scaling the instruction window for out-of-order processors.”
• Virtualizing transactional memory (2005, unknown): “Others [1, 23] have discussed hardware filter implementations.”
• ReStore: symptom based soft error detection in microprocessors (2005, background): “Proposed future architectures clearly reflect the trend of more speculation and longer checkpointing intervals [1].”