G. Sohi
Hardware and Architecture · 2000–2006
A researcher in the Science corpus: 3 papers; trusts 28 researchers and is trusted by 2 researchers here, as inferred from the citation graph.
Subfields
- Hardware and Architecture — 29 citations into it
- Computer Networks and Communications — 26 citations into it
- Electrical and Electronic Engineering — 9 citations into it; #9,739 of 16,539 by trust here, #12,727 by citations
Whom G. Sohi trusts overall
Their strongest outbound trust, strongest first, inferred from their citations.
- Moinuddin K. Qureshi
- Peter J. Denning
- Milo M. K. Martin
- Bradford M. Beckmann
- Changkyu Kim
- A. KleinOsowski
- David A. Wood
- Seongbeom Kim
- G. Suh
- Zeshan A. Chishti
Who trusts G. Sohi overall
Papers from G. Sohi's perspective
Ordered by how strongly the researchers G. Sohi trusts endorse each paper. Same corpus, a different order for every researcher.
- POWER4 system microarchitecture (IBM Journal of Research and Development)
- Fair cache sharing and partitioning in a chip multiprocessor architecture (Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.)
- Piranha: a scalable architecture based on single-chip multiprocessing (Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201))
- The future of wires (Proceedings of the IEEE)
- An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (ASPLOS X)
- Optimizing replication, communication, and capacity allocation in CMPs (International Symposium on Computer Architecture)
- Symbiotic jobscheduling for a simultaneous mutlithreading processor (SIGP)
- Balancing thoughput and fairness in SMT processors (2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.)
- Managing Wire Delay in Large Chip-Multiprocessor Caches (Micro)
- A new memory monitoring scheme for memory-aware scheduling and partitioning (Proceedings Eighth International Symposium on High Performance Computer Architecture)
Their papers
- A static power model for architects (2000) — 435 citations
- Cooperative Caching for Chip Multiprocessors (2006) — 424 citations
- Execution-based prediction using speculative slices (2001) — 327 citations