Adaptive insertion policies for high performance caching

By Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer. International Symposium on Computer Architecture, 2007

760 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/bcf8e55257c234c4ab21580776c677ffca341ec5

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Citations in the corpus

The evicted-address filter: A unified mechanism to address both cache pollution and thrashing (2012, methodology): “When following BIP, this can lead to high-reuse blocks getting repeatedly inserted with the bimodal insertion policy, causing a low cache hit rate.”
Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript (2015, methodology): “Moreover, Ivy Bridge, Haswell and Skylake use adaptive cache replacement policies which only behave as pseudo-LRU in some situations [33].”
DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors (2018, background): “, 16 times more edges than vertices), prefetching and scan- and thrash- resistant policies [26], [45] further reduce the need for cache resident read-only data.”
Base-delta-immediate compression: Practical data compression for on-chip caches (2012, background): “While caches have a number of design parameters and there is a large body of work on using cache hierarchies more effectively (e.g., [11, 17, 20, 21]), one key property of a cache that has a major impact on performance, die area, and power consumption is its capacity .”
Flush+Flush: A Fast and Stealthy Cache Attack (2015, background): “Typical replacement policies are least-recently used (LRU), variants of LRU and bimodal insertion policy where the CPU can switch between the two strategies to achieve optimal cache usage [32].”
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches (2009, background): “The recently proposed Dynamic Insertion Policy (DIP) technique can insert lines directly into the least-recently-used position to minimize the residency time of such dead-on-arrival lines [35].”
Cache-Conscious Wavefront Scheduling (2012, background): “There is a body of work attempting to increase cache hit rate by improving the replacement policy (e.g., [21] [34] among many others).”
SHiP: Signature-based Hit Predictor for high performance caching (2011, methodology): “SHiP is a more sophisticated cache insertion mechanism that makes more accurate re-reference predictions than recent cache insertion policy proposals [10, 27, 32].”
MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency (2018, background): “Cache insertion policies that account for cache thrashing [55, 56, 108], future reuse [116, 117], or inter-application interference [144] work well for CPU applications, but previous works have shown that some of these policies can be ineffective for GPU applications [16, 74].”
Tiered-latency DRAM: A low latency and low cost DRAM architecture (2013, background): “, [8, 17, 18, 36, 37, 38, 46]) have proposed sophisticated cache management policies in the context of processor SRAM caches.”