Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling

By Moinuddin K. Qureshi, J. Karidis, Michele M. Franceschini, Vijayalakshmi Srinivasan, Luis A. Lastras, B. Abali. Micro, 2009

759 citations recorded by the source corpus.

Subfields: Computer Networks and Communications, Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/2fc8a439f0f73462f875870c403c90ea1fb99e41

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Citations in the corpus

Memory persistency (2014, background): “While important, previous work suggests efﬁcient hardware to mitigate write-endurance concerns [24].”
Page placement in hybrid memory systems (2011, methodology): “FGWL inspired Start-Gap [27], a technique that applies a simple algebraic function to transform a logical memory address into a physical one.”
Overcoming the challenges of crossbar resistive memory architectures (2015, methodology): “While some recent prototypes of ReRAM are optimized for density trading off latency (e.g., a 32 Gb part from SanDisk [24] targeted as flash replacement), the technology can also be leveraged to build low latency memories.”
PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory (2016, neutral): “The reported endurance of ReRAM is up to 10(12) [21], [22], making the lifetime issue of ReRAM-based memory less concerned than PCM based main memory whose endurance has been assumed between 10(6)-10(8) [23].”
PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning (2017, background): “More details on the technology could be found in [1, 35, 36, 37, 38, 39, 40, 41, 42].”
RowHammer: A Retrospective (2019, background): “[202], [204], [245], [253], [254], [259], STT-MRAM [61], [137], and RRAM/ReRAM/memristors [246] are likely to exhibit similar and perhaps even more exacerbated reliability”
SCMFS: A file system for Storage Class Memory (2011, background): “Several wear-leveling schemes to protect PCM devices from normal applications and even malicious attacks have been proposed [15, 16, 22, 28].”
Recent Progress in Phase-Change Memory Technology (2016, background): “Efficient ECC and wear-leveling schemes [110] also help keep area efficiency—the fraction of CMOS real-estate used for memory devices as opposed to peripheral circuits—high.”
Emerging Memory Technologies: Recent Trends and Prospects (2016, background): “With the smart architectural wear-leveling techniques [53], the requirement of the cycling endurance for the main memory system can be reduced to 10(10) cycles; PCRAM/RRAM may meet this requirement with the help of a strong error-correct code.”
In-Memory Big Data Management and Processing: A Survey (2015, background): “[208], which can be easily hidden from the software design, while”