Yuejian Xie

Hardware and Architecture · 2009

A researcher in the Science corpus: 1 paper; trusts 5 researchers and is trusted by 7 researchers here, as inferred from the citation graph.

Subfields

Whom Yuejian Xie trusts overall

Their strongest outbound trust, strongest first, inferred from their citations.

  1. Moinuddin K. Qureshi
  2. Todd M. Austin
  3. Yale N. Patt
  4. Aamer Jaleel
  5. Daniel N. Lynch
  6. Dhruba Chandra
  7. Seongbeom Kim
  8. Onur Mutlu

Who trusts Yuejian Xie overall

  1. Ripal Nathuji
  2. Vivek Seshadri
  3. Aman Kansal
  4. Onur Mutlu
  5. Carole-Jean Wu
  6. Alireza Ghaffarkhah
  7. Mengjia Yan
  8. Michael A. Kozuch

Papers from Yuejian Xie's perspective

Ordered by how strongly the researchers Yuejian Xie trusts endorse each paper. Same corpus, a different order for every researcher.

  1. Fair cache sharing and partitioning in a chip multiprocessor architecture (Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.)
  2. Balancing thoughput and fairness in SMT processors (2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS.)
  3. A Case for MLP-Aware Cache Replacement (International Symposium on Computer Architecture)
  4. Dead-block prediction & dead-block correlating prefetchers (Proceedings 28th Annual International Symposium on Computer Architecture)
  5. Adaptive insertion policies for managing shared caches (International Conference on Parallel Architectures and Compilation Techniques)
  6. Adaptive insertion policies for high performance caching (International Symposium on Computer Architecture)
  7. Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches (Micro)
  8. MiBench: A free, commercially representative embedded benchmark suite (Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538))
  9. Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems (2008 IEEE 14th International Symposium on High Performance Computer Architecture)
  10. Predicting inter-thread cache contention on a chip multi-processor architecture (International Symposium on High-Performance Computer Architecture)

Their papers