A first-order superscalar processor model

By Tejas Karkhanis, James E. Smith. Proceedings. 31st Annual International Symposium on Computer Architecture, 2004., 2004

321 citations recorded by the source corpus.

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An Evaluation of High-Level Mechanistic Core Models (2014, methodology): “The performance of the microprocessor core is analyzed at the dispatch stage, in contrast to the issue stage that was the focus of previous work [Karkhanis and Smith 2004].”
Efficiently exploring architectural design spaces via predictive modeling (2006, background): “[18] T. Karkhanis and J. Smith.”
An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness (2009, background): “[15] T. S. Karkhanis and J. E. Smith.”
Accurate and efficient regression modeling for microarchitectural performance and power prediction (2006, background): “Nussbaum, Karkhanis, and Smith have examined similar statistical approaches for simulating superscalar and symmetric multiprocessor systems [11, 7].”
A Case for MLP-Aware Cache Replacement (2006, methodology): “The analytical model of out-of-order superscalar processors proposed by Karkhanis and Smith [11] provides fundamental insight into how parallelism in L2 misses can reduce the cycles per instruction incurred due to L2 misses.”
Optimizing User Satisfaction of Mobile Workloads Subject to Various Sources of Uncertainties (2019, background): “of the control variables [1], [2], [3], [4], [5], [10].”