Soft error rate mitigation techniques for modern microcircuits

By David, Mavis, P. Eaton. 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), 2002

368 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/e87aa5237814e8f20ae981639d6ec7cc87f11343

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Citations in the corpus

Single Event Transients in Digital CMOS—A Review (2013, methodology): “Critical transient width for un-attenuated propagation as a function of technology scaling, from [33].”
Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction (2013, background): “Another challenge to soft error rate prediction when considering MCU response in memories is that the count of memory cells in an MCU is a distribution, even with a single ion in a single direction [28], [62].”
Gate sizing to radiation harden combinational logic (2006, background): “In the next decade, technology trends—smaller feature sizes, lower voltage levels, higher operating frequencies, and reduced logic depth—are projected to cause an increase in the soft error failure rate in core combinational logic in integrated circuits [5], [18], [22], [33].”
Basic mechanisms and modeling of single-event upset in digital microelectronics (2003, background): “Temporal sampling circuit approaches have been developed that prevent the propagation of SETs and also provide the equivalent of triple spatial redundancy [164].”
Current and Future Challenges in Radiation Effects on CMOS Electronics (2010, methodology): “Due to both their greater ability to propagate in high-speed circuits and their higher probability of capture by subsequent storage elements such as latches, DSETs have been predicted to become endemic in deep submicron digital ICs [56].”
On-Chip Characterization of Single-Event Transient Pulsewidths (2006, background): “SETs result from the generation of electron-hole pairs and subsequent collection of charge by a circuit node.”
Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy lon and Proton Irradiation—Implications for Digital SETs (2006, background): “Our results (full and open diamonds for respectively bulk and SOI devices) are superimposed on circuit simulations from [8] and mixedmode simulations from [9].”
Production and propagation of single-event transients in high-speed digital logic ICs (2004, methodology): “Our results suggest that such schemes may be better suited to SOI ICs than to bulk ICs due to the much shorter transient widths expected in SOI devices.”
Radiation-induced soft errors in advanced semiconductor technologies (2005, background): “At an increased cost, even more robustness can be built-in if time and spatial multiplexed designs are used [47], [48].”
Digital Single Event Transient Trends With Technology Node Scaling (2006, background): “The latch structure achieves triple spatial redundancy via temporal sampling [6].”