Basic mechanisms and modeling of single-event upset in digital microelectronics

By Paul E. Dodd, Lloyd W. Massengill. 2003

1,189 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering, Hardware and Architecture

View Paper: https://www.semanticscholar.org/paper/9b7ddcd5b5816ab62f9b95b24c04e4dc5492953d

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In Electrical and Electronic Engineering

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Citations in the corpus

Radiation-induced soft errors in advanced semiconductor technologies (2005, background): “There are a plethora of radiation effects in semiconductor devices that vary in magnitude from data disruptions to permanent damage ranging from parametric shifts to complete device failure [1], [2].”
Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies (2007, background): “Technology scaling has precipitated higher operating speeds, lower operating voltages, and lower operating noise margins; all of which contribute to reduced switching energies, allowing legitimate logic signals to be readily overwhelmed by single-event-induced charge-collection transients [4].”
Present and Future Non-Volatile Memories for Space (2010, background): “Radiation sensitivity is determined by the storage mechanism, the feature size, the array architecture, and quite often by the building blocks of the peripheral circuitry, for both Total Ionizing Dose (TID) and Single Event Effects (SEE).”
Single Event Transients in Digital CMOS—A Review (2013, background): “Many works have highlighted the transient and charge collection mechanisms in reverse-biased junctions and isolated CMOS transistors ([56], [57], and references herein].”
Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction (2013, background): “While the Dodd and Massengill paper [1] provides a detailed summary of the charge collection mechanisms for single-event effects, this paper will summarize the main mechanisms as related to multiple-node charge collection and the indirect well-collapse source injection mechanism not provided in [1].”
Gate sizing to radiation harden combinational logic (2006, background): “…the exclusion of radiation-sensitive circuit styles (such as dynamic logic and non-complementary metal–oxide semiconductor (non-CMOS) styles) and the incorporation of sufficient functional margin in circuit designs to account for anticipated shifts in circuit characteristics [7], [19], [34].”