The future of wires

By Ron Ho, K. Mai, Mark A. Horowitz. Proceedings of the IEEE, 2001

1,573 citations recorded by the source corpus.

Subfields: Electrical and Electronic Engineering

View Paper: https://www.semanticscholar.org/paper/b9a115194ea5c9b4830dd175fa59a3d779100a8d

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In Electrical and Electronic Engineering

Citations in the corpus

Cooperative Caching for Chip Multiprocessors (2006, background): “In future technology, on-chip wire delay [63] will increase to a point that cross-chip cache accesses are far more expensive than local cache accesses.”
StreamIt: A Language for Streaming Applications (2002, methodology): “For this purpose, we developed StreamIt implementations of four applications: 1) A GSM Decoder, which takes GSM-encoded parameters as inputs, and uses these to synthesize audible speech[11], 2) A system from the Polymorphic Computing Architecture”
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory (2006, methodology): “At such integration levels, it is imperative to employ parallelism to effectively utilize the transistors [12].”
Analysis of power consumption on switch fabrics in network routers (2002, neutral): “The wire capacitance Cwire is a function of wire-length and coupling capacitance between adjacent wires [5].”
Theory of latency-insensitive design (2001, background): “Furthermore, while the number of gates reachable in a cycle will not change significantly and the on-chip bandwidth that wires provide will continue to grow, the percentage of the die reachable within one clock cycle will decrease dramatically: we will soon reach a point where more gates can be fit ”
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0 (2007, background): “The resistance and capacitance per unit length are governed by the following equations [17]:”
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches (2002, methodology): “Delays measured in FO4 are independent of technology; we model one FO4 as 360 picoseconds times the transistor's effective gate length in microns [11].”
Core fusion: accommodating software diversity in chip multiprocessors (2007, background): “Assuming a 65nm technology, a 4GHz clock, and 48ps/mm delay for a buffered global wire [21], we find that it is possible to propagate signals over a distance of 5.”
Express virtual channels: towards the ideal interconnection fabric (2007, background): “INTRODUCTION Driven by technology limitations to wire scaling and increasing bandwidth demands [1,2], packet-switched on-chip networks are fast replacing shared buses and dedicated wires as the de facto interconnection fabric in general-purpose chip multi-processors (CMPs) [3, 4] and application-spe”
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation (2009, background): “These long interconnects are quickly becoming a performance impediment in terms of communication latency and power [4].”
Three-dimensional integrated circuits (2006, background): “However, increasing wiring complexity and challenges in improving wire delay to keep up with intrinsic gate delay are key issues for BEOL technology [12].”
Managing Wire Delay in Large Chip-Multiprocessor Caches (2004, background): “Design partitioning, along with the integr tion of more metal layers, allows wire dimensions t decrease slower than transistor dimensions, thus keep wire delay controllable for short distances [20, 42].”
Smart Memories: a modular reconfigurable architecture (2000, background): “Second, their globally shared resource models (shared multi-ported registers and memory) will be increasingly difficult to implement in future technologies in which on-chip communication costs are appreciable [ 7 ,8].”