Theory of latency-insensitive design

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"It's a small world after all": NoC performance optimization via long-range link insertion (2006, background): “The use of repeaters with at least two-flit buffering capabilities guarantees latency-insensitive operation, as discussed in [7] and [8].”
NoC synthesis flow for customized domain specific multiprocessor systems-on-chip (2005, background): “This requires the system to be made of modules whose behavior does not depend on the latency of the communication channels (latency insensitive operation) [40].”
Xpipes: a network-on-chip architecture for gigascale systems-on-chip (2004, background): “This requires the system to be composed of modules whose behavior does not depend on the latency of input communication channels [34].”
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives (2009, background): “Different from general application-specific integrated circuits, floorplanning for NoCs may eventually consider the placement of routers and repeaters for latency insensitive operation [28].”
Key research problems in NoC design: a holistic perspective (2005, background): “3 Proposed Approaches & Open Problems Floorplanning for NoCs needs to consider placement of routers and repeaters for latency insensitive operation [10,36].”