Analysis of power consumption on switch fabrics in network routers

By Terry Tao Ye, Giovanni De Micheli, Luca Benini. Proceedings - Design Automation Conference, 2002

484 citations recorded by the source corpus.

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Energy-aware mapping for tile-based NoC architectures under performance constraints (2003, background): “(Note that the authors in [7] assume the buffers are implemented in SRAM or DRAM.”
A detailed and flexible cycle-accurate Network-on-Chip simulator (2013, background): “Prior research has shown that input buffers dominate the area and power of NoC routers [24], [25] .”
A survey on techniques for improving the energy efficiency of large-scale distributed systems (2014, background): “Ye et al. [Ye et al. 2002] studied four widely-used switch fabrics, namely crossbar, fully-connected, Banyan and Batcher-Banyan.”
Energy- and performance-aware mapping for regular NoC architectures (2005, background): “[9] proposed a model for energy consumption of network routers.”
Orion: a power-performance simulator for interconnection networks (2002, methodology): “As their goal was neither in building a tool for enabling fast architectural-level exploration, nor in enabling architectural-level research into powerefficient mechanisms, they adopted models based on transistor count [14], switch width [26] (which can only be used to derive average power estimates”
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers (2006, background): “A signal would require multiple clock cycles to traverse the length of a large System-on-Chip (SoC).”